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ORCID28th Hot Chips Symposium 2016: Cupertino, CA, USA
- 2016 IEEE Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August 21-23, 2016. IEEE 2016, ISBN 978-1-5090-6208-9
- J. Thomas Pawlowski:
Memory as we approach a new horizon. 1-23 - Jin Kim:
The future of graphic and mobile memory for new applications. 1-25 - Kevin Tran:
The era of high bandwidth memory. 1-22 - Suresh Ramalingam:
HBM package integration: Technology trends, challenges and applications. 1-17 - Allen Rush:
Memory technology and applications. 1-14 - Larry Yang:
3D sensors for the rest of us. 1-14 - Bernd Buxbaum:
VR and AR anytime and everywhere: Contributions of PMD depth sensing to an evolving ecosystem. 1-19 - David Moloney:
HW acceleration for volumetric applications. 1-19 - Dor Zepeniuk:
Inuitive breakthrough solution for AR and VR worlds. 1-14 - Ivan Dryanovski:
3D reconstruction with tango. 1-24 - Rafael Spring:
Mobile 3D capture for professional applications. 1-38 - Stefan Rusu:
Welcome to 2016 Hot Chips. 1-10 - Jem Davies:
The bifrost GPU architecture and the ARM Mali-G71 GPU. 1-31 - John Danskin, Denis Foley:
Pascal GPU with NVLink. 1-24 - Nigel Stephens:
ARMv8-A next-generation vector architecture for HPC. 1-31 - Tsung-Yao Lin, Ming-Hsien Lee, Loda Chou, Clavin Peng, Jih-Ming Hsu, Jia-Ming Chen, John-CC Chen, Alex Chiou, Artis Chiu, David Lee, Carrie Huang, Kenny Lee, TzuHeng Wang, Wei-Ting Wang, Yenchi Lee, Chi-Hui Wang, Pao-Ching Tseng, Ryan Chen, Kevin Jou:
Helio X20: The first tri-gear mobile SoC with CorePilot™ 3.0 technology. 1-24 - Brad Burgess:
Samsung exynos M1 processor. 1-18 - Peter Barry:
Design and development of a an ultra-low power Intel architecture MCU class SoCs. 1-29 - Andi Skende:
Introducing "parker": Next-generation tegra system-on-chip. 1-17 - Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, Huazhong Yang:
From model to FPGA: Software-hardware co-design for efficient neural network acceleration. 1-27 - Yair Siegel:
The path to embedded vision & AI using a low power vision DSP. 1-28 - Greg Efland, Sandip Parikh, Himanshu Sanghavi, Aamir Farooqui:
High performance DSP for vision, imaging and neural networks. 1-30 - Mu-Shan Lin, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y.-H. Chen, C.-C. Kuo, Shih-Peng Tai, Kazuyoshi Yamada:
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package. 1-32 - Radhakrishnan Nagarajan, Sudeep Bhoja, Tom Issenhuth:
100Gbit/s, 120km, PAM 4 based switch to switch, layer 2 silicon photonics based optical interconnects for datacenters. 1-17 - Emanuele Mandelli:
Quantum dot based imagers for multispectral cameras and sensors. 1-30 - Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Mohammad Shahrad
, Samuel Payne, David Wentzlaff:
Piton: A 25-core academic manycore research processor. 1-38 - Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
KiloCore: A 32 nm 1000-processor array. 1-23 - David Moloney:
Embedded deep neural networks: "The cost of everything and the value of nothing". 1-20 - Kathirgamar Aingaran, Sumti Jairath, David Lutz:
Software in Silicon in the Oracle SPARC M7 processor. 1-31 - Jian Ouyang, Wei Qi, Yong Wang, YichenTu, Jing Wang, Bowen Jia:
SDA: Software-Defined Accelerator for general-purpose big data analysis system. 1-23 - Ittai Anati, David Blythe, Jack Doweck, Hong Jiang, Wen-Fu Kao, Julius Mandelblat, Lihu Rappoport, Efraim Rotem, Ahmad Yasin:
Inside 6th gen Intel® Core™: New microarchitecture code named skylake. 1-39 - Brian W. Thompto:
POWER9: Processor for the cognitive era. 1-19 - Mike Clark:
A new ×86 core architecture for the next generation of computing. 1-19 - Kyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Hoi-Jun Yoo:
An intelligent ADAS processor with real-time semi-global matching and intention prediction for 720p stereo vision. 1 - Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally:
Deep compression and EIE: Efficient inference engine on compressed deep neural network. 1-6 - Ben Eckermann:
QORIQ® LS1012A: Big things in small packages: 64-bit core in a sub-10mm package. 1-9 - Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi:
A dynamically scheduled architecture for the synthesis of graph methods. 1-7 - Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an interactive synthesis flow. 1 - Tony Nowatzki, Karthikeyan Sankaralingam:
Modularizing the microprocessor core to outperform traditional out-of-order. 1-4 - Phillip Stanley-Marbell, Pier Andrea Francese, Martin C. Rinard:
Encoder logic for reducing serial I/O power in sensors and sensor hubs. 1-2 - Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten:
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. 1 - Cheng C. Wang, Dejan Markovic:
Reconfigure your RTL with EFLX join the SoC revolution. 1-5 - Tamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana:
Task parallel programming model + hardware acceleration = performance advantage. 1 - Yuta Tokusashi, Hiroki Matsutani:
NOSQL hardware appliance with multiple data structure. 1 - Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg:
AnyCore-1: A comprehensively adaptive 4-way superscalar processor. 1 - Léonie Buckley, Sam Caulfield, David Moloney:
MvEcho - acoustic response modelling for auralisation. 1 - Léonie Buckley, Sam Caulfield, David Moloney:
MvEcho. 1-6 - Luca Puglia, Mircea Ionica, Giancarlo Raiconi, David Moloney:
Passive dense stereo vision on the Myriad2 VPU. 1-5
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