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ORCIDJuan Salamanca 0001
Person information
- affiliation: São Paulo State University, Brazil
- affiliation: UNICAMP, Campinas, Brazil
Other persons with the same name
- Juan Salamanca 0002
![[0000-0002-4868-171X]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-4868-171X")
— University of Illinois at Urbana-Champaign, IL, USA (and 1 more) - Juan Salamanca 0003 — Universitat Pompeu Fabra, Music Technology Group. Barcelona, Spain
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2020 – today
- 2023
[c11]Juan Salamanca, Alexandro Baldassin:
How to Efficiently Parallelize Irregular DOACROSS Loops Using Fine Granularity and OpenMP Tasks: The SPEC mcf Case. IWOMP 2023: 81-96- [i1]Juan Salamanca, Alexandro Baldassin:
Evaluating the Performance of Speculative DOACROSS Loop Parallelization with taskloop. CoRR abs/2302.05506 (2023) - 2022
- [c10]Juan Salamanca:
Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory. ISPDC 2022: 83-90 - [c9]Juan Salamanca, Alexandro Baldassin:
Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP. IWOMP 2022: 50-64 - 2021
- [c8]Juan Salamanca, Alexandro Baldassin:
Improving Speculative taskloop in Hardware Transactional Memory. IWOMP 2021: 3-17 - 2020
- [c7]Juan Salamanca, Alexandro Baldassin:
Using Hardware Transactional Memory to Implement Speculative Privatization in OpenMP. LCPC 2020: 57-73
2010 – 2019
- 2019
- [c6]Juan Salamanca, Alexandro Baldassin:
A Proposal for Supporting Speculation in the OpenMP taskloop Construct. IWOMP 2019: 246-261 - 2018
- [j1]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. IEEE Trans. Parallel Distributed Syst. 29(2): 466-480 (2018) - [c5]Luis Mattos, Divino Cesar S. Lucas, Juan Salamanca, Joao P. L. de Carvalho, Márcio Machado Pereira, Guido Araujo:
DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability. SBAC-PAD 2018: 29-32 - 2017
- [c4]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. Euro-Par 2017: 607-621 - 2016
- [c3]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. IPDPS 2016: 586-595 - 2015
- [c2]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware Transactional Memory to Enable Speculative Trace Optimization. SBAC-PAD (Workshops) 2015: 1-6 - 2014
- [c1]Juan Salamanca, Luis Mattos, Guido Araujo:
Loop-Carried Dependence Verification in OpenMP. IWOMP 2014: 87-102
Coauthor Index
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