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Gaoming Du
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2020 – today
- 2024
- [j12]Peiyi Teng, Gaoming Du, Zhenmin Li, Xiaolei Wang, Yongsheng Yin:
High-speed hardware accelerator based on brightness improved by Light-DehazeNet. J. Real Time Image Process. 21(3): 87 (2024) - [j11]Jingwei Ren, Gaoming Du, Zhenmin Li, Xianhu Jia, Qiuzhu Liao, Xiaolei Wang, Duoli Zhang:
An Efficient Ring Polynomial Multiplication Accelerator for Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 415-419 (2024) - [c17]Gaoming Du, Zhuo Chen, Zhenmin Li, Xiaolei Wang, Duoli Zhang:
A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature. ACM Great Lakes Symposium on VLSI 2024: 258-262 - 2023
- [j10]Zhenmin Li, Jingwei Ren, Gaoming Du, Zhenxing Tu, Xiaolei Wang, Yongsheng Yin, Yiming Ouyang:
An Area-Efficient Large Integer NTT-Multiplier Using Discrete Twiddle Factor Approach. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 751-755 (2023) - 2022
- [j9]Zhenmin Li, Yuqing Ma, Gaoming Du, Xiaolei Wang, Yukun Song, Duoli Zhang:
RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC. IEEE Des. Test 39(6): 79-89 (2022) - [j8]Gaoming Du, Bangyi Chen, Zhenmin Li, Zhenxing Tu, Junjie Zhou, Shenya Wang, Qinghao Zhao, Yongsheng Yin, Xiaolei Wang:
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree. ACM Trans. Reconfigurable Technol. Syst. 15(3): 30:1-30:20 (2022) - 2021
- [j7]Gaoming Du, Jiting Wu, Hongfang Cao, Kun Xing, Zhenmin Li, Duoli Zhang, Xiaolei Wang:
A Real-Time Effective Fusion-Based Image Defogging Architecture on FPGA. ACM Trans. Multim. Comput. Commun. Appl. 17(3): 93:1-93:21 (2021) - [c16]Shijie Hu, Gaoming Du, Jiashen Li, Zhenmin Li, Wei Ni, Yongsheng Yin, Xiaolei Wang:
Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture. ASICON 2021: 1-4 - 2020
- [j6]Yiming Ouyang, Wu Zhou, Sheng Li, Zhilu Wang, Huaguo Liang, Gaoming Du:
Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC. J. Circuits Syst. Comput. 29(10): 2050171:1-2050171:27 (2020) - [j5]Gaoming Du, Yifan Cao, Zhenmin Li, Duoli Zhang, Li Wang, Yu-Kun Song, Yiming Ouyang:
A low-latency DMM-1 encoder for 3D-HEVC. J. Real Time Image Process. 17(3): 691-702 (2020)
2010 – 2019
- 2019
- [j4]Yiming Ouyang, Zhe Li, Jianhua Li, Chenglong Sun, Huaguo Liang, Gaoming Du:
CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness. Integr. 69: 75-84 (2019) - [j3]Gaoming Du, Guanyu Liu, Zhenmin Li, Yifan Cao, Duoli Zhang, Yiming Ouyang, Minglun Gao, Zhonghai Lu:
SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method. ACM J. Emerg. Technol. Comput. Syst. 15(3): 28:1-28:26 (2019) - [c15]Gaoming Du, Chao Tian, Zhenmin Li, Duoli Zhang, Yongsheng Yin, Yiming Ouyang:
Efficient Softmax Hardware Architecture for Deep Neural Networks. ACM Great Lakes Symposium on VLSI 2019: 75-80 - [c14]Gaoming Du, Zhenwen Yang, Zhenmin Li, Duoli Zhang, Yongsheng Yin, Zhonghai Lu:
NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator. ICCD 2019: 173-176 - 2017
- [j2]Yiming Ouyang, Jian Da, Xiumin Wang, Qianqian Han, Huaguo Liang, Gaoming Du:
A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC. J. Circuits Syst. Comput. 26(4): 1750059:1-1750059:19 (2017) - [c13]Gaoming Du, Shibi Ma, Zhenmin Li, Zhonghai Lu, Yiming Ouyang, Minglun Gao:
SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress). CASES 2017: 8:1-8:2 - [c12]Gaoming Du, Yongliang Zhang, Zhenmin Li, Guanyu Liu, Duoli Zhang, Yiming Ouyang:
On the Accuracy of Stochastic Delay Bound for Network on Chip. NOCS 2017: 14:1-14:8 - 2016
- [j1]Yiming Ouyang, Qi Chen, Xiumin Wang, Xiaoye Ouyang, Huaguo Liang, Gaoming Du:
AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip. J. Circuits Syst. Comput. 25(6): 1650050:1-1650050:15 (2016) - [c11]Gaoming Du, Yanghao Ou, Xiangyang Li, Ping Song, Zhonghai Lu, Minglun Gao:
OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction. DATE 2016: 1000-1005 - 2015
- [c10]Alberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu:
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls. ISVLSI 2015: 404-409 - 2014
- [c9]Gaoming Du, Miao Li, Zhonghai Lu, Minglun Gao, Chunhua Wang:
An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs. NOCS 2014: 49-56 - 2012
- [c8]Gaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio, Minglun Gao:
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing. CODES+ISSS 2012: 123-132 - 2010
- [c7]Wei Yi, Hongbing Pan, Peng Pan, Li Li, Minglun Gao, Ning Hou, Gaoming Du, Duoli Zhang:
Application-level pipelining on Hierarchical NoC. ISCAS 2010: 3873-3876
2000 – 2009
- 2009
- [c6]Chun-Ping Qin, Duoli Zhang, Gaoming Du, Minglun Gao, Yu-Kun Song:
VLSI Architecture of Video Post-Processing System for MPEG/H.26X. NCM 2009: 1520-1525 - 2008
- [c5]Luofeng Geng, Gaoming Du, Duoli Zhang, Minglun Gao, Ning Hou, Yu-Kun Song:
Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA. APCCAS 2008: 1264-1267 - [c4]Duoli Zhang, Yu-Kun Song, Gaoming Du, Yuanjie Zhai:
A technique of automatic monitor generation based on FSM. APCCAS 2008: 1775-1778 - [c3]Yong-Sheng Yin, Gaoming Du, Yu-Kun Song:
Study on the Multi-pipeline Reconfigurable Computing System. CSSE (4) 2008: 122-125 - [c2]Gaoming Du, Duoli Zhang, Yu-Kun Song, Minglun Gao, Luofeng Geng, Ning Hou:
Scalability Study on Mesh Based Network on Chip. PACIIA (2) 2008: 681-685 - 2007
- [c1]Yongsheng Yin, Li Li, Minglun Gao, Gaoming Du, Yu-Kun Song:
On the Implementation of Virtual Array Using Configuration Plane. APPT 2007: 199-208
Coauthor Index
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last updated on 2024-06-19 21:53 CEST by the dblp team
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