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ORCIDN. Pete Sedcole
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2010 – 2019
- 2010
[j5]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4(3): 196-210 (2010)- [j4]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43(2): 188-201 (2010) - [c24]Edward A. Stott, Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238
2000 – 2009
- 2009
- [j3]Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 10:1-10:22 (2009) - [c23]N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung:
Compensating for variability in FPGAs by re-mapping and re-placement. FPL 2009: 613-616 - [c22]Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung:
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296 - 2008
- [j2]N. Pete Sedcole, Peter Y. K. Cheung:
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ACM Trans. Reconfigurable Technol. Syst. 1(2): 10:1-10:28 (2008) - [c21]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 - [c20]N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Measuring and modeling FPGA clock variability. FPGA 2008: 258 - [c19]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420 - [c18]Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole:
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 - [c17]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 - [c16]Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112 - [c15]N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224 - [c14]N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 - [c13]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 - [c12]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 - [c11]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 - 2007
- [j1]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1003-1016 (2007) - [c10]N. Pete Sedcole, Peter Y. K. Cheung:
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA 2007: 178-187 - [c9]Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT 2007: 17-23 - [c8]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 - 2006
- [c7]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 - [c6]N. Pete Sedcole, Peter Y. K. Cheung:
Within-die delay variability in 90nm FPGAs and beyond. FPT 2006: 97-104 - [c5]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 - 2005
- [c4]N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght:
Modular Partial Reconfiguration in Virtex FPGAs. FPL 2005: 211-216 - 2004
- [c3]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 - [c2]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 - 2003
- [c1]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615
Coauthor Index
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