"Modelling and compensating for clock skew variability in FPGAs."

N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung (2008)

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DOI: 10.1109/FPT.2008.4762386

access: closed

type: Conference or Workshop Paper

metadata version: 2019-04-03

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N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224

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