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2020 – today
- 2023
[c50]Juan Pablo Romero Bermudez
, Luis A. Plana, Andrew Rowley, Mikael Hessel, Jens Egholm Pedersen, Steve B. Furber, Jörg Conradt:
A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems. ICONS 2023: 28:1-28:8- [c49]Gopinath Mahale, Tejas Limbasiya, Muhammad Asad Aleem, Luis A. Plana, Aleksandar Duricic, Alireza Monemi, Xabier Abancens, Teresa Cervero, John D. Davis:
Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress. ISC Workshops 2023: 472-485 - 2020
- [j24]Luis A. Plana, Jim D. Garside, Jonathan Heathcote, Jeffrey Pepper, Steve Temple, Simon Davidson, Mikel Luján, Steve B. Furber:
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. IEEE Access 8: 84918-84928 (2020) - [j23]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. Simul. Model. Pract. Theory 103: 102088 (2020)
2010 – 2019
- 2019
- [j22]Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr:
Dynamic Power Management for Neuromorphic Many-Core Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2973-2986 (2019) - [i3]Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumaerker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr:
Dynamic Power Management for Neuromorphic Many-Core Systems. CoRR abs/1903.08941 (2019) - [i2]Oliver Rhodes, Luca Peres, Andrew G. D. Rowley, Andrew Gait, Luis A. Plana, Christian Y. A. Brenninkmeijer, Steve B. Furber:
Real-Time Cortical Simulation on Neuromorphic Hardware. CoRR abs/1909.08665 (2019) - 2018
- [j21]Robert James, Jim D. Garside, Luis A. Plana, Andrew Rowley, Steve B. Furber:
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. IEEE Trans. Biomed. Circuits Syst. 12(5): 1018-1026 (2018) - [c48]Markos Kynigos, Javier Navaridas, Luis A. Plana, Steve B. Furber:
Network-on-chip evaluation for a novel neural architecture. CF 2018: 216-219 - [c47]Amirreza Yousefzadeh, Mikel Soto, Teresa Serrano-Gotarredona, Francesco Galluppi, Luis A. Plana, Steve B. Furber, Bernabé Linares-Barranco:
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker. ISCAS 2018: 1-4 - [i1]Andrew G. D. Rowley, Christian Y. A. Brenninkmeijer, Simon Davidson, Donal Fellows, Andrew Gait, David R. Lester, Luis A. Plana, Oliver Rhodes, Alan B. Stokes, Steve B. Furber:
SpiNNTools: The Execution Engine for the SpiNNaker Platform. CoRR abs/1810.06835 (2018) - 2017
- [j20]Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco:
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Trans. Biomed. Circuits Syst. 11(5): 1133-1147 (2017) - [c46]Robert James, Jim D. Garside, Michael Hopkins, Luis A. Plana, Steve Temple, Simon Davidson, Steve B. Furber:
Parallel distribution of an inner hair cell and auditory nerve model for real-time application. BioCAS 2017: 1-4 - [c45]Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch:
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL 2017: 1-8 - [c44]Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber:
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS 2017: 1 - [c43]Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber:
Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS 2017: 1-4 - [c42]Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco:
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ISCAS 2017: 1 - [c41]Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco:
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ISCAS 2017: 1-4 - 2016
- [j19]Amirreza Yousefzadeh, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco:
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 763-767 (2016) - [c40]Indar Sugiarto, Gengting Liu, Simon Davidson, Luis A. Plana, Steve B. Furber:
High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing. IPCCC 2016: 1-8 - 2015
- [j18]Javier Navaridas, Mikel Luján, Luis A. Plana, Steve Temple, Steve B. Furber:
SpiNNaker: Enhanced multicast routing. Parallel Comput. 45: 49-66 (2015) - [j17]Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, Jim D. Garside, Kier J. Dugan, Luis A. Plana, Steve Temple:
SpiNNaker - Programming Model. IEEE Trans. Computers 64(6): 1769-1782 (2015) - [c39]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. FCCM 2015: 96 - [c38]Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Francesco Galluppi, Luis A. Plana, Stephen B. Furber:
ConvNets experiments on SpiNNaker. ISCAS 2015: 2405-2408 - [c37]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Analysis of FPGA and software approaches to simulate unconventional computer architectures. ReConFig 2015: 1-8 - 2014
- [j16]Steve B. Furber, Francesco Galluppi, Steve Temple, Luis A. Plana:
The SpiNNaker Project. Proc. IEEE 102(5): 652-665 (2014) - [c36]Javier Navaridas, Mikel Luján, Luis A. Plana, Steve Temple, Steve B. Furber:
On generating multicast routes for SpiNNaker. Conf. Computing Frontiers 2014: 2:1-2:10 - [c35]Francesco Galluppi, Christian Denk, Matthias C. Meiner, Terrence C. Stewart, Luis A. Plana, Chris Eliasmith, Stephen B. Furber, Jörg Conradt:
Event-based neural computing on an autonomous mobile platform. ICRA 2014: 2862-2867 - 2013
- [j15]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber:
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits 48(8): 1943-1953 (2013) - [j14]Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang:
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. 39(11): 693-708 (2013) - [j13]Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown:
Overview of the SpiNNaker System Architecture. IEEE Trans. Computers 62(12): 2454-2467 (2013) - [c34]Johannes Partzsch, Christian Mayr, Bernhard Vogginger, René Schüffny, Alexander D. Rast, Luis A. Plana, Steve B. Furber:
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems. ECCTD 2013: 1 - [c33]Christian Denk, Francisco Llobet-Blandino, Francesco Galluppi, Luis A. Plana, Steve B. Furber, Jörg Conradt:
Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System. ICANN 2013: 467-474 - [c32]Alexander D. Rast, Johannes Partzsch, Christian Mayr, Johannes Schemmel, Stefan Hartmann, Luis A. Plana, Steve Temple, David R. Lester, René Schüffny, Steve B. Furber:
A location-independent direct link neuromorphic interface. IJCNN 2013: 1-8 - 2012
- [j12]Alexander D. Rast, Javier Navaridas, Xin Jin, Francesco Galluppi, Luis A. Plana, José Miguel-Alonso, Cameron Patterson, Mikel Luján, Steve B. Furber:
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. Int. J. Parallel Program. 40(6): 553-582 (2012) - [j11]Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber:
Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. 72(11): 1507-1520 (2012) - [c31]Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana:
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC 2012: 49-56 - [c30]Francesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, Steve B. Furber:
A hierachical configuration system for a massively parallel neural hardware platform. Conf. Computing Frontiers 2012: 183-192 - [c29]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber:
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4 - [c28]Javier Navaridas, Mikel Luján, Luis A. Plana, José Miguel-Alonso, Stephen B. Furber:
Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System. HPCC-ICESS 2012: 1-8 - [c27]Alexander D. Rast, Luis A. Plana, Stephen R. Welbourne, Stephen B. Furber:
Event-driven MLP implementation on neuromimetic hardware. IJCNN 2012: 1-8 - 2011
- [j10]Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge:
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7(4): 17:1-17:18 (2011) - [j9]Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Cameron Patterson, Thomas Sharp, David R. Lester, Steve B. Furber:
Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. Neural Networks 24(9): 961-978 (2011) - [j8]Mukaram M. Khan, Alexander D. Rast, Javier Navaridas, X. Jin, Luis A. Plana, Mikel Luján, Steve Temple, Cameron Patterson, Dominic Richards, John V. Woods, José Miguel-Alonso, Stephen B. Furber:
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. Parallel Comput. 37(8): 392-409 (2011) - [c26]Thomas Sharp, Luis A. Plana, Francesco Galluppi, Steve B. Furber:
Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker. ICONIP (3) 2011: 424-430 - [c25]Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp, Steve B. Furber:
An event-driven model for the SpiNNaker virtual synaptic channel. IJCNN 2011: 1967-1974 - 2010
- [j7]Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve B. Furber:
Modeling Spiking Neural Networks on SpiNNaker. Comput. Sci. Eng. 12(5): 91-97 (2010) - [j6]Linda E. M. Brackenbury, Luis A. Plana, Jeffrey Pepper:
System-on-Chip Design and Implementation. IEEE Trans. Educ. 53(2): 272-281 (2010) - [j5]Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona:
Asynchronous Data-Driven Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1093-1106 (2010) - [c24]Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber:
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. Conf. Computing Frontiers 2010: 11-20 - [c23]Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber:
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. Conf. Computing Frontiers 2010: 21-30 - [c22]Andrew D. Brown, Steve B. Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester:
A communication infrastructure for a million processor machine. Conf. Computing Frontiers 2010: 75-76 - [c21]Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve B. Furber:
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. Conf. Computing Frontiers 2010: 89-90 - [c20]Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana:
Description-Level Optimisation of Synthesisable Asynchronous Circuits. DSD 2010: 441-448 - [c19]Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber:
Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. ISPDC 2010: 9-16
2000 – 2009
- 2009
- [j4]Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana:
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. Fundam. Informaticae 95(1): 53-72 (2009) - [c18]Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana:
Fault Tolerant Delay Insensitive Inter-chip Communication. ASYNC 2009: 77-84 - [c17]Luis A. Tarazona, Doug A. Edwards, Luis A. Plana:
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. DSD 2009: 627-634 - [c16]Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve B. Furber:
Understanding the interconnection network of SpiNNaker. ICS 2009: 286-295 - [c15]Alexander D. Rast, Mukaram M. Khan, Xin Jin, Luis A. Plana, Steve B. Furber:
A universal abstract-time platform for real-time neural networks. IJCNN 2009: 2611-2618 - [c14]Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber:
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. ISPDC 2009: 54-61 - [c13]Shufan Yang, Stephen B. Furber, Luis A. Plana:
Adaptive admission control on the SpiNNaker MPSoC. SoCC 2009: 243-246 - 2008
- [c12]Shufan Yang, Steve B. Furber, Yebin Shi, Luis A. Plana:
An admission control system for QoS provision on a best-effort GALS interconnect. ACSD 2008: 200-207 - [c11]Sam Taylor, Doug A. Edwards, Luis A. Plana:
Automatic Compilation of Data-Driven Circuits. ASYNC 2008: 3-14 - [c10]Andrew D. Brown, David R. Lester, Luis A. Plana, Steve B. Furber, Peter R. Wilson:
SpiNNaker: The Design Automation Problem. ICONIP (2) 2008: 1049-1056 - [c9]Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, Eustace Painkras, Stephen B. Furber:
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. IJCNN 2008: 2849-2856 - [c8]Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu:
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216 - 2007
- [j3]Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang:
A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Des. Test Comput. 24(5): 454-463 (2007) - [c7]Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley:
Performance-driven syntax-directed synthesis of asynchronous processors. CASES 2007: 43-47 - 2005
- [c6]Luis A. Plana, Sam Taylor, Doug A. Edwards:
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. ICCD 2005: 703-710 - 2004
- [c5]W. J. Bainbridge, Luis A. Plana, Stephen B. Furber:
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE 2004: 274-279 - 2003
- [j2]Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu:
SPA - a secure Amulet core for smartcard applications. Microprocess. Microsystems 27(9): 431-446 (2003) - [c4]Z. C. Yu, Stephen B. Furber, Luis A. Plana:
An Investigation into the Security of Self-Timed Circuits. ASYNC 2003: 206-215 - 2002
- [c3]W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Peter A. Riocreux, Luis A. Plana:
SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210
1990 – 1999
- 1998
- [j1]Luis A. Plana, Steven M. Nowick:
Architectural optimization for low-power nonpipelined asynchronous systems. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 56-65 (1998) - [c2]Luis A. Plana, Stephen H. Unger:
Pulse-mode macromodular systems. ICCD 1998: 348-353 - 1996
- [c1]Luis A. Plana, Steven M. Nowick:
Concurrency-oriented optimization for low-power asynchronous systems. ISLPED 1996: 151-156
Coauthor Index
Steve B. Furber
aka: Stephen B. Furber
aka: Stephen B. Furber
[c50] [j24] [j22] [i3] [i2] [j21] [c48] [c47] [i1] [j20] [c46] [c45] [c44] [c43] [c42] [c41] [j19] [c40] [j18] [j17] [c38] [j16] [c36] [c35] [j15] [j14] [j13] [c34] [c33] [c32] [j12] [j11] [c31] [c30] [c29] [c28] [c27] [j10] [j9] [j8] [c26] [c25] [j7] [c24] [c23] [c22] [c21] [c19] [j4] [c18] [c16] [c15] [c14] [c13] [c12] [c10] [c9] [c8] [j3] [c5] [c4]
Alex Rast
aka: Alexander D. Rast
aka: Alexander D. Rast
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