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ORCIDDeshanand P. Singh
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Journal Articles
- 2024
[j5]Rui Ma
, Jia-Ching Hsu, Ali Mansoorshahi, Joseph Garvey, Michael Kinsner, Deshanand P. Singh, Derek Chiou:
Primate: A Framework to Automatically Generate Soft Processors for Network Applications. IEEE Comput. Archit. Lett. 23(1): 57-60 (2024)- 2013
- [j4]Doris Chen, Deshanand P. Singh:
Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications. ACM Trans. Archit. Code Optim. 9(4): 43:1-43:25 (2013) - 2007
- [j3]Deshanand P. Singh, Stephen Dean Brown:
An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. 40(2): 167-173 (2007) - [j2]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1196-1210 (2007) - [j1]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 895-903 (2007)
Conference and Workshop Papers
- 2024
- [c26]Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna:
PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF 2024 - 2015
- [c25]Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski:
High-Level Design Tools for Floating Point FPGAs. FPGA 2015: 9-12 - 2014
- [c24]Mohamed S. Abdelfattah, Andrei Hagiescu, Deshanand P. Singh:
Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL. IWOCL 2014: 4:1-4:9 - 2013
- [c23]Doris Chen, Deshanand P. Singh:
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. ASP-DAC 2013: 297-304 - [c22]Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling:
Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA 2013: 5-6 - 2012
- [c21]Doris Chen, Deshanand P. Singh:
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. FPL 2012: 5-12 - [c20]Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh:
From opencl to high-performance hardware on FPGAS. FPL 2012: 531-534 - 2011
- [c19]Doris Chen, Deshanand P. Singh:
Line-level incremental resynthesis techniques for FPGAs. FPGA 2011: 133-142 - 2010
- [c18]Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz:
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA 2010: 167-176 - [c17]Doris Chen, Deshanand P. Singh:
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). FPL 2010: 125-132 - 2007
- [c16]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177 - 2006
- [c15]Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142 - [c14]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8 - 2005
- [c13]Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Two-stage physical synthesis for FPGAs. CICC 2005: 171-178 - [c12]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. DAC 2005: 427-432 - [c11]Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438 - [c10]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24 - [c9]Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown:
Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38 - [c8]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450 - 2004
- [c7]Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown:
The Quartus University Interface Program: enabling advanced FPGA research. FPT 2004: 225-230 - 2003
- [c6]Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown:
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33 - [c5]Deshanand P. Singh, Stephen Dean Brown:
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50 - 2002
- [c4]Deshanand P. Singh, Stephen Dean Brown:
Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76 - [c3]Deshanand P. Singh, Stephen Dean Brown:
Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126 - [c2]Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759 - 2001
- [c1]Deshanand P. Singh, Stephen Dean Brown:
The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169
Parts in Books or Collections
- 2016
- [p1]Deshanand P. Singh, Peter Yiannacouras:
OpenCL. FPGAs for Software Programmers 2016: 97-114
Informal and Other Publications
- 2024
- [i2]Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah:
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. CoRR abs/2403.12981 (2024) - 2023
- [i1]Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna:
A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. CoRR abs/2311.09445 (2023)
Coauthor Index
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