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ORCIDChunsheng Liu 0002
Person information
- affiliation: Alibaba Inc., DAMO Academy, Sunnyvale, CA, USA
- affiliation (PhD 2003): Duke University, Durham, NC, USA
Other persons with the same name
- Chunsheng Liu — disambiguation page
- Chunsheng Liu 0001
![[0000-0001-5516-2486]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5516-2486")
— Shandong University, School of Control Science and Engineering, Jinan, China - Chunsheng Liu 0003 — National University of Defense Technology, Hefei, Anhui, China
- Chunsheng Liu 0004 — Nanjing University of Aeronautics and Astronautics, College of Automation Engineering, Jiangsu, China (and 1 more)
- Chunsheng Liu 0005 (aka: Chun-Sheng Liu 0005) — Heilongjiang Institute of Science and Technology, School of Mechanical Engineering, Harbin, China
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2020 – today
- 2023
[j9]Fei Su, Chunsheng Liu, Haralampos-G. Stratigopoulos:
Special Issue on Testability and Dependability of Artificial Intelligence Hardware. IEEE Des. Test 40(2): 5-7 (2023)- [j8]Fei Su, Chunsheng Liu, Haralampos-G. Stratigopoulos:
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives. IEEE Des. Test 40(2): 8-58 (2023) - 2022
- [j7]Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty:
C-Testing and Efficient Fault Localization for AI Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2348-2361 (2022) - 2020
- [c10]Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty:
C-Testing of AI Accelerators *. ATS 2020: 1-6
2000 – 2009
- 2006
- [j6]Érika F. Cota, Chunsheng Liu:
Constraint-Driven Test Scheduling for NoC-Based Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2465-2478 (2006) - [c9]Chunsheng Liu, Zach Link, Dhiraj K. Pradhan:
Reuse-based test access and integrated test scheduling for network-on-chip. DATE 2006: 303-308 - [c8]Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51 - 2005
- [j5]Dhiraj K. Pradhan, Chunsheng Liu:
EBIST: a novel test generator with built-in fault detection capability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1457-1466 (2005) - [j4]Chunsheng Liu, Krishnendu Chakrabarty:
Design and analysis of compact dictionaries for diagnosis in scan-BIST. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 979-984 (2005) - [c7]Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota:
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. VTS 2005: 349-354 - 2004
- [j3]Chunsheng Liu, Krishnendu Chakrabarty:
Compact Dictionaries for Fault Diagnosis in Scan-BIST. IEEE Trans. Computers 53(6): 775-780 (2004) - [j2]Chunsheng Liu, Krishnendu Chakrabarty:
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1447-1459 (2004) - [c6]Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton:
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. ISVLSI 2004: 173-178 - [c5]Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan:
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. ITC 2004: 1369-1378 - 2003
- [j1]Chunsheng Liu, Krishnendu Chakrabarty:
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 593-604 (2003) - [c4]Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty:
EBIST: A Novel Test Generator with Built-In Fault Detection Capability. DATE 2003: 10224-10229 - [c3]Chunsheng Liu, Krishnendu Chakrabarty:
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. DATE 2003: 10230-10237 - [c2]Chunsheng Liu, Krishnendu Chakrabarty:
Compact Dictionaries for Fault Diagnosis in BIST. ISQED 2003: 105-110 - 2002
- [c1]Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel:
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. DATE 2002: 382-386
Coauthor Index
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