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Li-Yang Hong
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2020 – today
- 2024
- [j4]Ping-Chun Wu, Jian-Wei Su
, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li
, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu
, Chih-Cheng Hsieh
, Kea-Tiong Tang
, Meng-Fan Chang
:
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits 59(1): 196-207 (2024) - [j3]Jinshan Yue
, Yongpan Liu
, Xiaoyu Feng
, Yifan He, Jingyu Wang
, Zhe Yuan, Mingtao Zhan
, Jiaxin Liu
, Jian-Wei Su
, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang
, Nan Sun, Chunmeng Dou
, Xueqing Li
, Ming Liu
, Huazhong Yang
:
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. IEEE J. Solid State Circuits 59(5): 1612-1627 (2024) - [j2]Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li
, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu
, Chih-Cheng Hsieh
, Kea-Tiong Tang
, Meng-Fan Chang
:
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits 59(7): 2297-2309 (2024) - 2023
- [j1]Jian-Wei Su
, Yen-Chi Chou, Ruhui Liu
, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li
, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si
, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh
, Kea-Tiong Tang
, Meng-Fan Chang
:
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58(3): 877-892 (2023) - [c3]Ping-Chun Wu, Jian-Wei Su
, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC 2023: 126-127 - 2022
- [c2]Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Li-Fan Chen, Yeh-Ning Jou, Shin-Cheng Lin, Walter Wohlmuth, Chih-Cherng Liao, Ching-Ho Li, Shoa-Chang Huang, Ke-Horng Chen
:
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. IRPS 2022: 2 - [c1]Ping-Chun Wu, Jian-Wei Su
, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang:
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC 2022: 1-3
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last updated on 2024-07-20 21:18 CEST by the dblp team
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