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"A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline ..."

Jian-Wei Su et al. (2023)

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DOI: 10.1109/JSSC.2022.3199077

access: closed

type: Journal Article

metadata version: 2023-08-28

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  dblp key:
  - journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23
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  - https://dblp.org/rec/journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58(3): 877-892 (2023)

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