"Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for ..."

B. Jhnanesh Somayaji, M. S. Bhat (2016)

> Home

Details and statistics

DOI: 10.1109/ISED.2016.7977057

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-01

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ised/SomayajiB16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ised/SomayajiB16
B. Jhnanesh Somayaji, M. S. Bhat:
Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. ISED 2016: 72-76

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.