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"14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor ..."

Jagadish Dasarahalli Narasimaiah, Mujoor Shankaranarayana Bhat (2018)

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DOI: 10.1049/IET-CDS.2018.5067

access: closed

type: Journal Article

metadata version: 2020-09-10

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Jagadish Dasarahalli Narasimaiah, Mujoor Shankaranarayana Bhat:
14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS. IET Circuits Devices Syst. 12(6): 671-680 (2018)

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