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ORCIDJie S. Hu
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- affiliation: New Jersey Institute of Technology, USA
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2010 – 2019
- 2012
[j13]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
:
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Comput. Digit. Tech. 6(1): 50-58 (2012)- [j12]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 643-654 (2012) - [c22]Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu:
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors. DFT 2012: 92-97 - 2011
- [c21]Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu:
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. ISVLSI 2011: 266-271 - 2010
- [j11]Joonho Kong, Johnsy K. John, Eui-Young Chung, Sung Woo Chung, Jie S. Hu:
On the Thermal Attack in Instruction Caches. IEEE Trans. Dependable Secur. Comput. 7(2): 217-223 (2010) - [c20]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI 2010: 310-315
2000 – 2009
- 2009
- [j10]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58(9): 1171-1184 (2009) - [j9]Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embed. Comput. Syst. 8(4): 27:1-27:30 (2009) - [j8]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras:
On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 953-963 (2009) - [c19]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung:
Exploiting narrow-width values for thermal-aware register file designs. DATE 2009: 1422-1427 - 2008
- [j7]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras:
Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocess. Microsystems 32(3): 171-182 (2008) - [j6]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1503-1507 (2008) - [c18]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI 2008: 81-86 - 2007
- [j5]Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
Optimising power efficiency in trace cache fetch unit. IET Comput. Digit. Tech. 1(4): 334-348 (2007) - [j4]Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu:
Reconfiguration support for vector operations. Int. J. High Perform. Syst. Archit. 1(2): 89-97 (2007) - [c17]Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu:
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA 2007: 61-70 - [c16]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras:
Asymmetrically Banked Value-Aware Register Files. ISVLSI 2007: 363-368 - [c15]Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu:
Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI 2007: 447-448 - [c14]Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu:
FPGA-based Vector Processing for Matrix Operations. ITNG 2007: 989-994 - 2006
- [c13]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras:
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN 2006: 281-290 - [c12]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS 2006: 14-20 - 2005
- [j3]Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Analyzing data reuse for cache reconfiguration. ACM Trans. Embed. Comput. Syst. 4(4): 851-876 (2005) - [c11]Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras:
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214 - [c10]Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Compiler-Directed Instruction Duplication for Soft Error Detection. DATE 2005: 1056-1057 - [c9]Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras:
Optimizing the Thermal Behavior of Subarrayed Data Caches. ICCD 2005: 625-630 - 2004
- [j2]Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Reducing instruction cache energy consumption using a compiler-based strategy. ACM Trans. Archit. Code Optim. 1(1): 3-33 (2004) - [c8]Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin:
Scheduling Reusable Instructions for Power Reduction. DATE 2004: 148-155 - [c7]Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin:
Exploring Wakeup-Free Instruction Scheduling. HPCA 2004: 232-243 - 2003
- [j1]Nam Sung Kim, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan:
Leakage Current: Moore's Law Meets Static Power. Computer 36(12): 68-75 (2003) - [c6]Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
Exploiting program hotspots and code sequentiality for instruction cache leakage management. ISLPED 2003: 402-407 - [c5]Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. ISVLSI 2003: 127-132 - 2002
- [c4]Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Power-Efficient Trace Caches. DATE 2002: 1091 - [c3]Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer:
Energy-conscious compilation based on voltage scaling. LCTES-SCOPES 2002: 2-11 - [c2]Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang:
Compiler-directed cache polymorphism. LCTES-SCOPES 2002: 165-174 - [c1]Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Compiler-directed instruction cache leakage optimization. MICRO 2002: 208-218
Coauthor Index
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