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ORCIDThomas Chiarella
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2010 – 2019
- 2019
[c9]Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marco Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi:
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS 2019: 1-7- 2017
- [c8]F. M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta:
On the ballistic ratio in 14nm-Node FinFETs. ESSDERC 2017: 176-179 - 2016
- [c7]Thomas Chiarella, S. Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, A. De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134 - 2015
- [c6]Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of fin shape variability on device performance towards 10nm node. ICICDT 2015: 1-4 - [c5]Ankush Chaudhary, Ben Kaczer, Philippe J. Roussel, Thomas Chiarella, Naoto Horiguchi, Souvik Mahapatra:
Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI. IRPS 2015: 3 - [c4]Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser
, Philippe J. Roussel, Stanislav Tyaginov, M. Bina, Yannick Wimmer, Luis-Miguel Procel, Lionel Trojman, Felice Crupi, G. Pitner, V. Putcha, Pieter Weckx, Erik Bury, Z. Ji, A. De Keersgieter, Thomas Chiarella, Naoto Horiguchi, Guido Groeseneken, Aaron Thean:
Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3 - 2013
- [c3]Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, A. De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha:
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC 2013: 159-162 - 2012
- [c2]Christoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck:
Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. ESSDERC 2012: 221-225
2000 – 2009
- 2009
- [c1]Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, C. Kerner, R. Dittrich, Michal Rakowski, C. Ortolland, L.-Å. Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann:
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? ESSCIRC 2009: 84-87
Coauthor Index
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