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ORCIDYu Cao 0001
- > Home > Persons > Yu Cao 0001
Publications
- 2023
[c128]Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Yu Cao:
Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling. ASICON 2023: 1-4- 2022
- [j68]Gokul Krishnan
, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 18(2): 34:1-34:22 (2022) - [c119]Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. ICCAD 2022: 8:1-8:9 - 2021
- [j64]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 20(5s): 68:1-68:24 (2021) - [c118]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration. ASICON 2021: 1-4 - [i16]Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan:
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR abs/2103.13813 (2021) - [i14]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR abs/2107.02358 (2021) - [i13]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR abs/2108.08903 (2021) - 2020
- [j63]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test 37(6): 79-87 (2020) - [j62]Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-Sun Seo, Yu Cao, Ümit Y. Ogras:
A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 362-375 (2020) - 2017
- [j45]Chengen Yang, Manqing Mao, Yu Cao, Chaitali Chakrabarti:
Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance. IEEE Trans. Multi Scale Comput. Syst. 3(1): 1-11 (2017) - [c92]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [i2]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j43]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 352-363 (2016) - [c79]Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS 2016: 2326-2329 - 2015
- [c74]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c72]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. ICCD 2015: 359-366 - [c68]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. SiPS 2015: 1-6 - 2014
- [j35]Chengen Yang, Yunus Emre, Zihan Xu, Hsing Min Chen, Yu Cao, Chaitali Chakrabarti:
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram. J. Signal Process. Syst. 76(2): 133-147 (2014) - [c62]Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao, Chaitali Chakrabarti:
Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. SiPS 2014: 139-144 - 2013
- [c60]Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao:
Compact modeling of STT-MTJ for SPICE simulation. ESSDERC 2013: 338-341 - 2012
- [j29]Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti:
Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding. EURASIP J. Adv. Signal Process. 2012: 211 (2012) - [c56]Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao:
Hierarchical modeling of Phase Change memory for reliable design. ICCD 2012: 115-120 - [c54]Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti:
An analytical approach to efficient circuit variability analysis in scaled CMOS design. ISQED 2012: 641-647 - [c52]Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti:
Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM. SiPS 2012: 114-119 - [c51]Yunus Emre, Chengen Yang, Ketul Sutaria, Yu Cao, Chaitali Chakrabarti:
Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques. SiPS 2012: 125-130
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