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Jie Zhang 0007
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Publications
- 2015
- [j6]Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra:
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1082-1095 (2015) - [i1]Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra:
Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. CoRR abs/1507.05679 (2015) - 2014
- [j5]Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli:
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. 10(4): 33:1-33:19 (2014) - 2013
- [c10]Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra:
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. DAC 2013: 105:1-105:10 - [c9]Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube circuits: opportunities and challenges. DATE 2013: 619-624 - 2012
- [j4]Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra:
Carbon Nanotube Robust Digital VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 453-471 (2012) - 2011
- [j3]Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang:
Robust System Design. IPSJ Trans. Syst. LSI Des. Methodol. 4: 2-30 (2011) - [j2]Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra:
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1103-1113 (2011) - [c8]Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. ICCAD 2011: 227-230 - 2010
- [c7]Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra:
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. DAC 2010: 889-892 - [c6]Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube circuits: Living with imperfections and variations. DATE 2010: 1159-1164 - 2009
- [j1]Jie Zhang, Nishant Patil, Subhasish Mitra:
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1307-1320 (2009) - [c5]Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra:
Carbon nanotube circuits in the presence of carbon nanotube density variations. DAC 2009: 71-76 - [c4]Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. DAC 2009: 304-309 - [c3]Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei:
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. DATE 2009: 436-441 - [c2]Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli:
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. DATE 2009: 616-621 - 2008
- [c1]Jie Zhang, Nishant Patil, Subhasish Mitra:
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. DATE 2008: 1009-1014
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