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ORCIDGregorio Cappuccino
Person information
- affiliation: Universita della Calabria, Cosenza, Italy
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Journal Articles
- 2014
[j10]Luca Magnelli, Francesco A. Amoroso, Felice Crupi, Gregorio Cappuccino
, Giuseppe Iannaccone:
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier. Int. J. Circuit Theory Appl. 42(9): 967-977 (2014)- 2012
- [j9]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Design approach for high-bandwidth low-power three-stage operational amplifiers. Int. J. Circuit Theory Appl. 40(3): 263-273 (2012) - [j8]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
A new efficient SC integrator scheme for high-speed low-power applications. Int. J. Circuit Theory Appl. 40(8): 733-744 (2012) - 2011
- [j7]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
Design criterion for high-speed low-power SC circuits. Int. J. Circuit Theory Appl. 39(10): 1067-1078 (2011) - 2010
- [j6]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. Microelectron. J. 41(7): 440-446 (2010) - [j5]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 618-630 (2010) - [j4]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1812-1813 (2010) - 2009
- [j3]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(12): 2569-2582 (2009) - 2008
- [j2]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 1-5 (2008) - 1998
- [j1]Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo:
High performance VLSI modules for division and square root. Microprocess. Microsystems 22(5): 239-246 (1998)
Conference and Workshop Papers
- 2012
- [c18]Stephen Williams, Anita N. Vasavada, Jacques Nicolas Beneat, Gregorio Cappuccino, David C. Lin, Warren A. Rosen, M. Eric Carr, Kirk Reinkens, Mingrui Zhang, Francesco A. Amoroso:
Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students. FIE 2012: 1-2 - 2009
- [c17]Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese:
Class-AB output stage design for high-speed three-stage op-amps. ICECS 2009: 1-4 - [c16]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers. ICECS 2009: 5-8 - [c15]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. ISCAS 2009: 3134-3137 - 2008
- [c14]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS 2008: 318-327 - 2007
- [c13]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Design methodology of nested-Miller amplifiers for small capacitive loads. ECCTD 2007: 655-658 - [c12]Davide Urbano, Emilio Arnieri, Gregorio Cappuccino, Giandomenico Amendola:
Integrated waveguides for ultra-high speed interconnects. Nano-Net 2007: 5 - [c11]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers. PATMOS 2007: 107-116 - 2006
- [c10]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS 2006: 311-318 - [c9]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS 2006: 524-531 - 2005
- [c8]Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo:
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS 2005: 329-336 - 2003
- [c7]Gregorio Cappuccino:
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. DSD 2003: 138-143 - [c6]Gregorio Cappuccino:
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects. ICECS 2003: 491-494 - 2002
- [c5]Gregorio Cappuccino, Giuseppe Cocorullo:
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. PATMOS 2002: 438-447 - 2001
- [c4]Gregorio Cappuccino, Giuseppe Cocorullo:
CMOS sizing rule for high performance long interconnects. DATE 2001: 817 - [c3]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino:
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS 2001: 723-727 - [c2]Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino:
Dynamic power of CMOS gates driving lossy transmission lines. ICECS 2001: 1579-1582 - 1999
- [c1]Gregorio Cappuccino, Giuseppe Cocorullo:
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. EUROMICRO 1999: 1204-1208
Coauthor Index
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