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ORCIDAndrea Pugliese 0002
Person information
- affiliation: University of Calabria, Department of Electronics, Computer Science and Systems, Italy
- not to be confused with: Andrea Pugliese 0001
Other persons with the same name
- Andrea Pugliese 0001
![[0000-0003-4385-958X]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-4385-958X")
— University of Calabria, Department of Electronics, Computer Science and Systems, Rende, Italy - Andrea Pugliese 0003 — University of Trento, Mathematics Department, Italy
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2010 – 2019
- 2012
[j8]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Design approach for high-bandwidth low-power three-stage operational amplifiers. Int. J. Circuit Theory Appl. 40(3): 263-273 (2012)- [j7]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
A new efficient SC integrator scheme for high-speed low-power applications. Int. J. Circuit Theory Appl. 40(8): 733-744 (2012) - 2011
- [j6]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
Design criterion for high-speed low-power SC circuits. Int. J. Circuit Theory Appl. 39(10): 1067-1078 (2011) - 2010
- [j5]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. Microelectron. J. 41(7): 440-446 (2010) - [j4]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 618-630 (2010) - [j3]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1812-1813 (2010)
2000 – 2009
- 2009
- [j2]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(12): 2569-2582 (2009) - [c9]Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese:
Class-AB output stage design for high-speed three-stage op-amps. ICECS 2009: 1-4 - [c8]Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino:
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers. ICECS 2009: 5-8 - [c7]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. ISCAS 2009: 3134-3137 - 2008
- [j1]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 1-5 (2008) - [c6]Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS 2008: 318-327 - 2007
- [c5]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Design methodology of nested-Miller amplifiers for small capacitive loads. ECCTD 2007: 655-658 - [c4]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers. PATMOS 2007: 107-116 - 2006
- [c3]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS 2006: 311-318 - [c2]Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS 2006: 524-531 - 2005
- [c1]Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo:
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS 2005: 329-336
Coauthor Index
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