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ORCID26th VLSI Design 2013: Pune, India
- 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-4639-9
- Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
:
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. 1-6 - Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran:
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. 7-12 - Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan:
Localized Heating for Building Energy Efficiency. 13-18 - Saptarshi Roy, Amit Patra, Partha Pratim Chakrabarti, Purnendu Sinha, Dipankar Das:
Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks. 19-24 - Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao:
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. 25-30 - Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha:
Energy-efficient and Secure Sensor Data Transmission Using Encompression. 31-36 - Abhijit Giri, S. K. Nandy:
Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. 37-42 - Sparsh Mittal, Zhao Zhang, Yanan Cao:
CASHIER: A Cache Energy Saving Technique for QoS Systems. 43-48 - Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia:
Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures. 49-54 - Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart:
A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. 55-59 - Supriya Aggarwal, Kavita Khare:
Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline. 60-65 - Maryamsadat Hashemian, Swarup Bhunia:
Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems. 66-71 - Aatmesh Shrivastava, Jagdish Nayayan Pandey, Brian P. Otis, Benton H. Calhoun:
A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node. 72-75 - Sanku Mukherjee, M. Thrivikraman M., Anil K. Goyal, Arul Sendhil:
A Novel Scheme to Reset through Clock. 76-79 - Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu:
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. 80-85 - Rahul Shrestha, Roy P. Paily:
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. 86-91 - B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. 92-97 - P. Deepa, C. Vasanthanayaki:
VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique. 98-102 - Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury:
Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. 103-108 - Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee:
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. 109-114 - Rajat Chauhan, Manigandan Selvam:
Input Referred Offset Reduction in Very High Speed Differential Receivers. 115-119 - Surhud Khare, Shailendra Jain:
Prospects of Near-Threshold Voltage Design for Green Computing. 120-124 - Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha:
PODIA: Power Optimization through Differential Imbalanced Amplifier. 125-129 - Cheekala Lovaraju, Ashis Maity, Amit Patra:
A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip Applications. 130-135 - Anvesha Amaravati, Maryam Shojaei Baghini:
A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit. 136-141 - Nitin Gupta, Phalguni Bala, Vijay Kumar Singh:
Area & Power Efficient 3.4Gbps/Channel HDMI Transmitter with Single-Ended Structure. 142-146 - Neeraj Mishra, Niraj K. Jha, Santanu Kapat, Amit Patra:
Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery. 147-152 - Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi:
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy. 153-157 - Prashant Dubey, Rashmi Agarwal:
38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS. 158-162 - Amiya Prasad Behera, Subhasis Sasmal, Prajit Nandi:
A Wide Range CMOS VCO for PLL Applications. 163-168 - Hyuksu Son, Woo Young Kim, Joo Young Jang, Hae Jin Lee, Inn Yeal Oh, Chul Soon Park:
A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX Applications. 169-172 - Abhirup Lahiri, Anurag Tiwari:
A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process. 173-178 - Somnath Kundu, Shouri Chatterjee:
A 44 GHz Quadrature Traveling Wave Oscillator. 179-184 - Rajath Vasudevamurthy, Bharadwaj Amrutur:
Multiphase Technique to Speed-up Delay Measurement via Sub-sampling. 185-190 - Vinay M. M., Roy Paily, Anil Mahanta:
Gain, NF and IIP3 Budgeting of LTE Receiver Front End. 191-196 - Debashis Banerjee, Aritra Banerjee, Abhijit Chatterjee:
Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation Control. 197-202 - Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Emerging Frontiers in Embedded Security. 203-208 - Debajit Bhattacharya, Ashis Maity, Amit Patra:
Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications. 209-214 - K. Naveen, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect. 215-220 - Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti:
Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators. 221-226 - Thannirmalai Somu Muthukaruppan, Tulika Mitra:
Lifetime Reliability Aware Architectural Adaptation. 227-232 - Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan:
Power Supply Efficiency Aware Server Allocation in Data Centers. 233-238 - Ons Mbarek, Alain Pegatoquet, Michel Auguin, Houssem Eddine Fathallah:
Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach. 239-244 - Ankit Kagliwal, Shankar Balachandran:
Measuring Area-Complexity Using Boolean Difference. 245-250 - Pavlos M. Mattheakis, Christos P. Sotiriou:
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. 251-256 - Raka Sardar, Ratna Mondal, Tuhina Samanta:
Geometry Independent Wirelength Estimation Method in VLSI Routing. 257-261 - Jim Monthie, Vineet Sreekumar, Ranjit Yashwante:
Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces. 262-266 - Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. 267-272 - Praveen Venkataramani, Vishwani D. Agrawal:
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. 273-278 - Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. 279-284 - Sukeshwar Kannan, Bruce C. Kim, Anurag Gupta, Friedrich Taenzler, Richard Antley, Ken Moushegian:
Physics Based Fault Models for Testing High-Voltage LDMOS. 285-290 - Kanad Basu, Prabhat Mishra, Priyadarsan Patra:
Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. 291-296 - Sanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan E. K., Arul Sendhil:
At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems. 297-301 - Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham:
Dynamic Trace Signal Selection for Post-Silicon Validation. 302-307 - Kamran Rahmani, Prabhat Mishra:
Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers. 308-313 - Sabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee:
VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests. 314-319 - Mingsong Chen, Prabhat Mishra:
Assertion-Based Functional Consistency Checking between TLM and RTL Models. 320-325 - Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee:
Formal Verification of Hardware / Software Power Management Strategies. 326-331 - M. Santhosh Prabhu, Pallab Dasgupta:
Model Checking Controllers with Predicate Inputs. 332-337 - Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of KPN Level Transformations. 338-343 - Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, Dallas Lea, D. Sciacca:
Hardware-corroborated Variability-Aware SRAM Methodology. 344-349 - Yang Yang, Niraj K. Jha:
Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. 350-355 - Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. 356-361 - Kartikeya Bhardwaj, Bharat M. Deshpande:
K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier. 362-367 - Md. Shamsujjoha, Hafiz Md. Hasan Babu:
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. 368-373 - Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya:
Microelectromechanical Longitudinal Resonator for Frequency Reference Applications. 374-379 - Ankush Jain, Ram Gopal:
Design and Simulation of Structurally Decoupled 4-DOF MEMS Vibratory Gyroscope. 380-385 - Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Sneak-path Testing of Memristor-based Memories. 386-391 - Ruchir Puri:
Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation. - Lou Scheffer:
Keynote talk: Deciphering the brain, cousin to the chip. - Vijaykrishnan Narayanan:
Keynote talk: Embedded vision systems. - Prabhat Avasare, Nitin Chandrachoodan:
Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon. - Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal:
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. - Bipin Rajendran:
Embedded tutorial - Can silicon machines match the efficiency of the human brain? - Moinuddin K. Qureshi:
Embedded tutorial - Emerging memory technologies: What it means for computer system designers.
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