"SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read ..."

Hyeyeong Lee, Joonhyung Kim, Jongsun Park (2022)

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DOI: 10.1109/ISOCC56007.2022.10031591

access: closed

type: Conference or Workshop Paper

metadata version: 2023-04-14

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Hyeyeong Lee, Joonhyung Kim, Jongsun Park:
SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. ISOCC 2022: 5-6

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