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Joo-Mi Cho

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2020 – today

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2024
[j2]
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Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Young-Jun Jeon, Jeeyoung Shin, Woong Choi, Junwon Jeong, Sung-Wan Hong:
A Simultaneous Energy Transferring SIBO Converter Achieving Low Ripple and High Efficiency for AMOLED Applications. IEEE J. Solid State Circuits 59(5): 1497-1508 (2024)
[c9]
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Hyo-Jin Park, Joo-Mi Cho, Chan-Ho Lee, Young-Ju Oh, Hyunwoo Jeong, Jun-Hyeok Yang, Jaeseung Lee, Sung-Wan Hong:
8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1. ISSCC 2024: 1-3
2023
[j1]
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  - journals/tie/ChoiBHKJYCPLPBOALH23
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Hyeon-Ji Choi, Chisung Bae, Yeunhee Huh, Sang Joon Kim, Seungchul Jung, Kye-Seok Yoon, Joo-Mi Cho, Hyo-Jin Park, Chan-Ho Lee, Su-Min Park, Esun Baik, Young-Ju Oh, Ho-Chan Ahn, Chan-Kyu Lee, Sung-Wan Hong:
An Ultra-Low Power Soft-Switching Self-Oscillating SIMO Converter for Implantable Stimulation Systems. IEEE Trans. Ind. Electron. 70(8): 8603-8608 (2023)
[c8]
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  - conf/esscirc/AhnCCLLH23
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Ho-Chan Ahn, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Chan-Kyu Lee, Sung-Wan Hong:
A 2 A Maximum Load Current Capable 0-to-1 μF Off-chip Capacitor N-type LDO using Dual Dynamic Negative Feedback Loop and an Improved Error Amplifier. ESSCIRC 2023: 249-252
[c7]
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  - conf/vlsit/LeePCCJH23
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Chan-Ho Lee, Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Young-Jun Jeon, Sung-Wan Hong:
A 1V 20.7μW Four-Stage Amplifier Capable of Driving a 4-to-12nF Capacitive Load with >1.07MHz GBW with an Improved Active Zero. VLSI Technology and Circuits 2023: 1-2
[c6]
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Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Sung-Wan Hong:
96.48% Peak-Efficiency Continuous-Current Step-Up Battery Charger (CC-SUBC) with Dual Energy-Harvesting Sources for Automotive Application. VLSI Technology and Circuits 2023: 1-2
2022
[c5]
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  - conf/isocc/OhPCCPLBLAH22
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Young-Ju Oh, Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan-Kyu Lee, Ho-Chan Ahn, Sung-Wan Hong:
A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops. ISOCC 2022: 231-232
2021
[c4]
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  - conf/asscc/ChoiCPH21
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Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Sung-Wan Hong:
An Output Capacitor-less Low-dropout Regulator using a Wide-range Single-stage Gain-boosted Error Amplifier and a Frequency-dependent Buffer with a Total Compensation Capacitance of 2.5 pF in 0.5 µm CMOS. A-SSCC 2021: 1-3
[c3]
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Joo-Mi Cho, Hyo-Jin Park, Hyunji Choi, Esun Baik, Jeeyoung Shin, Sung-Wan Hong:
A 100-MHz 81.2% All-Paths Inductor-Connected Buck-Converter with Balanced Conduction-Losses and Continuous Path-Currents. ESSCIRC 2021: 323-326
[c2]
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Hyo-Jin Park, Joo-Mi Cho, Hyunji Choi, Esun Baik, Jeeyoung Shin, Sung-Wan Hong:
A 18 µA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 µm. ESSCIRC 2021: 399-402
[c1]
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  - conf/vlsic/ChoPH21
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Joo-Mi Cho, Hyo-Jin Park, Sung-Wan Hong:
A 0.93-μW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops. VLSI Circuits 2021: 1-2

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