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ORCIDDipankar Pal
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2020 – today
- 2024
[c15]Surajit Bhattacherjee, Daksh Shah, Dipankar Pal:
Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. AICAS 2024: 477-481- [i1]Kasi Bandla, Dipankar Pal:
Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform. CoRR abs/2402.14519 (2024) - 2023
- [c14]Surajit Bhattacherjee, Dipankar Pal:
IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off. ICNC 2023: 626-629 - 2022
- [j5]Aloke Saha
, Rakesh Kumar Singh, Dipankar Pal:
Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier. Microelectron. J. 119: 105318 (2022) - 2021
- [j4]Aloke Saha, Narendra Deo Singh, Dipankar Pal:
Efficient ternary comparator on CMOS technology. Microelectron. J. 109: 105005 (2021) - [c13]Taaha Nizam, Vallabhuni Vijay, Avireni Srinivasulu, Dipankar Pal:
Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII. TENCON 2021: 7-10 - 2020
- [c12]Akhilesh G. Naik, Debarshi Deka, Dipankar Pal:
ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [c11]T. Nagateja, Avireni Srinivasulu, Dipankar Pal:
RF Harvesting System for Low-Power Applications Using FinFETs. ICCE 2019: 1-6 - 2018
- [j3]Dipankar Pal, Nabin Ghoshal:
Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal Noise. Wirel. Pers. Commun. 100(2): 505-518 (2018) - [c10]Dipankar Pal, Akhilesh G. Naik:
Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier. ICICDT 2018: 29-32 - [c9]Suparno Pal, Dipankar Pal:
Modified Time-Based Current Mode ADC. TENCON 2018: 1342-1345 - 2017
- [c8]Avireni Srinivasulu, Dipankar Pal:
CCII+ based dual square-and-triangular waveform generator. ECAI 2017: 1-6 - 2014
- [c7]Anush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal:
A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC. ISED 2014: 219-223 - 2013
- [j2]Aloke Saha, Dipankar Pal, Mahesh Chandra:
Low-power 6-GHz wave-pipelined 8b x 8b multiplier. IET Circuits Devices Syst. 7(3) (2013) - 2010
- [c6]Chutham Sawigun, Dipankar Pal, Andreas Demosthenous:
A wide-input linear range sub-threshold transconductor for sub-Hz filtering. ISCAS 2010: 1567-1570
2000 – 2009
- 2009
- [j1]Dipankar Pal, Avireni Srinivasulu, Basab Bijoy Pal, Andreas Demosthenous, B. N. Das:
Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity. IEEE Trans. Instrum. Meas. 58(7): 2174-2180 (2009) - [c5]Dipankar Pal, Avireni Srinivasulu, Manish Goswami:
Novel Current-mode Waveform Generator with Independent Frequency and Amplitude Control. ISCAS 2009: 2946-2949 - 2007
- [c4]Chutham Sawigun, Jirayuth Mahattanakul, Andreas Demosthenous, Dipankar Pal:
A low-power CMOS analog voltage buffer using compact adaptive biasing. ECCTD 2007: 1-4 - [c3]Chutham Sawigun, Andreas Demosthenous, Dipankar Pal:
A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier. ECCTD 2007: 751-754 - 2005
- [c2]Robert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter J. Langlois, Nick Donaldson:
10-channel very low noise ENG amplifier system using CMOS technology. ISCAS (1) 2005: 748-751 - [c1]Robert Rieger, Dipankar Pal, John Taylor, Peter J. Langlois:
Two preamplifiers for non-invasive on-chip recording of neural-signals. ISCAS (3) 2005: 2727-2730
Coauthor Index
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