"Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines."

Zhenyu Xu et al. (2025)

> Home

Details and statistics

DOI: 10.1145/3706628.3708822

access: closed

type: Conference or Workshop Paper

metadata version: 2025-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/XuYZCYW25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/XuYZCYW25
Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei:
Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines. FPGA 2025: 172-178

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.