"FPGA test time reduction through a novel interconnect testing scheme."

Stuart McCracken, Zeljko Zilic (2002)

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DOI: 10.1145/503048.503069

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Stuart McCracken, Zeljko Zilic:
FPGA test time reduction through a novel interconnect testing scheme. FPGA 2002: 136-144

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