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Publication search results
found 113 matches
- 1995
- Mark D. Aagaard, Carl-Johan H. Seger:
The formal verification of a pipelined double-precision IEEE floating-point multiplier. ICCAD 1995: 7-10 - Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
Addressing high frequency effects in VLSI interconnects with full wave model and CFH. ICCAD 1995: 53-56 - Hussain Al-Asaad, John P. Hayes:
Design verification via simulation and automatic test pattern generation. ICCAD 1995: 174-180 - Pranav Ashar, Sharad Malik:
Fast functional simulation using branching programs. ICCAD 1995: 408-412 - Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. ICCAD 1995: 612-617 - R. Iris Bahar, Fabio Somenzi:
Boolean techniques for low power driven re-synthesis. ICCAD 1995: 428-432 - Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh:
Estimation and bounding of energy consumption in burst-mode control circuits. ICCAD 1995: 26-33 - Krishna P. Belkhale, Alexander J. Suess:
Timing analysis with known false sub graphs. ICCAD 1995: 736-740 - Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash:
Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278 - Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken:
Efficient orthonormality testing for synthesis with pass-transistor selectors. ICCAD 1995: 256-263 - Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok:
Be careful with don't cares. ICCAD 1995: 83-86 - Randal E. Bryant:
Binary decision diagrams and beyond: enabling technologies for formal verification. ICCAD 1995: 236-243 - Kai-Yuan Chao, D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725 - Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325 - Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427 - Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686 - David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation. ICCAD 1995: 650-655 - Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee:
Diagnosis of realistic bridging faults with single stuck-at information. ICCAD 1995: 185-192 - Pai H. Chou, Ross B. Ortega, Gaetano Borriello:
Interface co-synthesis techniques for embedded systems. ICCAD 1995: 280-287 - Tan-Li Chou, Kaushik Roy:
Statistical estimation of sequential circuit activity. ICCAD 1995: 34-37 - Mike Chou, Jacob K. White:
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. ICCAD 1995: 40-44 - Amit Chowdhary, John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming. ICCAD 1995: 346-352 - Edmund M. Clarke, Masahiro Fujita, Xudong Zhao:
Hybrid decision diagrams. ICCAD 1995: 159-163 - Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. ICCAD 1995: 568-574 - Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71 - Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
Synthesizing Petri nets from state-based models. ICCAD 1995: 164-171 - Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen:
A high-level design and optimization tool for analog RF receiver front-ends. ICCAD 1995: 550-553 - Peter Dahlgren:
A multiple-dominance switch-level model for simulation of short faults. ICCAD 1995: 674-680 - Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715 - Giri Devarayanadurg, Mani Soma:
Dynamic test signal design for analog ICs. ICCAD 1995: 627-630
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