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Keikichi Tamaru
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2000 – 2009
- 2000
- [c24]Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru:
A method for linking process-level variability to system performances. ASP-DAC 2000: 547-552
1990 – 1999
- 1999
- [c23]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451 - 1998
- [j5]Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru:
A memory efficient array architecture for real-time motion estimation. Syst. Comput. Jpn. 29(9): 13-20 (1998) - [j4]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 400-405 (1998) - [c22]Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru:
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP 1998: 2673-2676 - [c21]Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru:
A new architecture for in-memory image convolution. ICASSP 1998: 3001-3004 - [c20]Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru:
Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544 - [c19]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226 - 1997
- [c18]Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru:
A functional memory type parallel processor for vector quantization. ASP-DAC 1997: 665-666 - [c17]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A current mode cyclic A/D converter with a 0.8 μm CMOS process. ASP-DAC 1997: 683-684 - [c16]Vasily G. Moshnyaga, Keikichi Tamaru:
A memory efficient array architecture for full-search block matching algorithm. ICASSP 1997: 4109-4112 - [c15]Vasily G. Moshnyaga, Keikichi Tamaru:
A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32 - 1996
- [c14]Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154- - 1995
- [j3]Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru:
Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Trans. Inf. Syst. 78-D(3): 252-255 (1995) - [j2]Farhad Fuad Islam, Keikichi Tamaru:
High speed merged array multiplication. J. VLSI Signal Process. 10(1): 41-52 (1995) - [c13]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A model-adaptable MOSFET parameter extraction system. ASP-DAC 1995 - [c12]Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru:
A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995 - [c11]Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427 - [c10]Kuei-Ming Lu, Keikichi Tamaru:
A New Algorithm for Sorting Problem with Reformed CAM. ISCAS 1995: 1045-1048 - [c9]Vasily G. Moshnyaga, Keikichi Tamaru:
A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563 - 1994
- [c8]Kuei-Ming Lu, Keikichi Tamaru:
Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP. ISPAN 1994: 119-126 - 1993
- [c7]Farhad Fuad Islam, Keikichi Tamaru:
High speed merged multiplication. ICASSP (1) 1993: 377-380 - [c6]Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru:
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103 - [c5]Farhad Fuad Islam, Keikichi Tamaru:
An Architecture for Intermediate Area-time Complexity Multiplier. ISCAS 1993: 1825-1828 - 1992
- [c4]Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura:
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192 - 1991
- [c3]Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru:
Branch-and-Bound Placement for Building Block Layout. DAC 1991: 433-439 - 1990
- [c2]M. Ohmura, Hiroto Yasuura, Keikichi Tamaru:
Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179
1980 – 1989
- 1987
- [j1]Keikichi Tamaru, Hidetoshi Onodera:
System design of a special-purpose computer for LSI design rule checking. Syst. Comput. Jpn. 18(2): 43-54 (1987)
1970 – 1979
- 1978
- [c1]Hajime lizuka, Yutaka Hayashi, Keikichi Tamaru, Hisashi Hara:
Development of a high-performance universal computing element - PULCE. AFIPS National Computer Conference 1978: 1255-1264
Coauthor Index
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