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Publication search results
found 116 matches
- 1996
- Emile H. L. Aarts, Gerben Essink, Erwin A. de Kock:
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors. ED&TC 1996: 460-466 - Mohamed Abid, Adel Changuel, Ahmed Amine Jerraya:
A Hardware/Software Codesign Case Study: Design of a Robot Arm Controller. ED&TC 1996: 599 - Michel Allemand, Solange Coupet-Grimal, Line Jakubiec, Jean-Luc Paillet:
A System for Modelling and Proving Circuits. ED&TC 1996: 605 - Bert Atzema, Taco Zwemstra:
Exploit Analog IFA to Improve Specification Based Tests. ED&TC 1996: 542-546 - Ahmed Riadh Baba-Ali, A. Farah:
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI. ED&TC 1996: 288-293 - Keith Baker:
IDDQ: you heard the hype, but what's really coming? ED&TC 1996: 116-119 - Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy:
A Fast Optimal Robust Path Delay Fault Testable Adder. ED&TC 1996: 491-499 - Armin Bender:
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System. ED&TC 1996: 275-281 - Reinaldo A. Bergamaschi, Salil Raje:
Observable Time Windows: Verifying the Results of High-Level Synthesis. ED&TC 1996: 350-356 - Ernst G. Bernard, Sven Simon, Josef A. Nossek:
Built-in self test architectures for multistage interconnection networks. ED&TC 1996: 176-180 - Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin:
Asynchronous SRT Dividers: The Real Cost. ED&TC 1996: 195-199 - Stephanus Büttgenbach, O. Than:
SUZANA: A 3D CAD Tool for Anisotropically Etched Silicon Microstructures. ED&TC 1996: 454-459 - Jordi Carrabina, L. Hébrard, Angel Merlos, Joaquín Saiz, J. Bausells:
Design Kit for Microsystems Design for an Enhanced CMOS Process. ED&TC 1996: 619 - Ales Casar, Zmago Brezocnik, Tatjana Kapus:
Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTL. ED&TC 1996: 606 - S. Caufape, Joan Figueras:
Power Optimization of Delay Constrained CMOS Bus Drivers. ED&TC 1996: 205-213 - P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC 1996: 79-87 - Wah Chan, Alex Orailoglu:
High-level synthesis of gracefully degradable ASICs. ED&TC 1996: 50-54 - Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. ED&TC 1996: 402-406 - Y. P. Chen, D. F. Wong:
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. ED&TC 1996: 230-236 - Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits. ED&TC 1996: 566-570 - R. A. Cobley:
Approaches to On-chip Testing of Mixed Signal Macros in ASICs. ED&TC 1996: 553-559 - J. L. Conesa:
Design challenges of high speed ATM communication ASICs. ED&TC 1996: 27-29 - Tom Conway, John Nelson:
VLSI Design of a High Speed Soft Decision Viterbi Detector. ED&TC 1996: 598 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study. ED&TC 1996: 610 - Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca:
Advanced Techniques for GA-based sequential ATPGs. ED&TC 1996: 375-379 - Francesco Corsi, Cristoforo Marzocca, S. Martino:
Assessing the Quality Level of Digital CMOS IC's under the Hypothesis of Non-Uniform Distribution of Fault Probabilities. ED&TC 1996: 72-78 - Olivier Coudert:
Gate Sizing: A General Purpose Optimization Approach. ED&TC 1996: 214-218 - Chryssa Dislis, Ian P. Jalowiecki:
Economics Modelling and Optimisation of MCM Test Strategies. ED&TC 1996: 615 - Rolf Drechsler, Bernd Becker, Stefan Ruppertz:
K*BMDs: A New Data Structure for Verification. ED&TC 1996: 2-8 - Alexander V. Drozd, Wael Hassonah, Michel Lobachov:
Hardware Check of Arithmetic Devices with Abridged Execution of Operations. ED&TC 1996: 611
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retrieved on 2024-09-23 14:50 CEST from data curated by the dblp team
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