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Publication search results
found 48 matches
- 1997
- Yves Audet, Glenn H. Chapman:
Yield improvement of a large area magnetic field sensor array using redundancy schemes. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 28-33 (1997) - Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 417-424 (1997) - Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan:
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 82-100 (1997) - Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò:
Gate-level power and current simulation of CMOS integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 473-488 (1997) - Alex R. Bugeja, W. Yang:
A reconfigurable VLSI coprocessing system for the block matching algorithm. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 329-337 (1997) - Jui-Ming Chang, Massoud Pedram:
Energy minimization using multiple supply voltages. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 436-443 (1997) - Samit Chaudhuri, S. A. Blthye, Robert A. Walker:
A solution methodology for exact design space exploration in a three-dimensional design space. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 69-81 (1997) - Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 175-185 (1997) - Pi-Yu Chung, Ibrahim N. Hajj:
Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 233-237 (1997) - Olivier Coudert:
Gate sizing for constrained delay/power/area optimization. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 465-472 (1997) - Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya:
Protocol selection and interface generation for HW-SW codesign. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 136-144 (1997) - G. Digele, S. Lindenkreuz, E. Kasper:
Fully coupled dynamic electro-thermal simulation. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 250-257 (1997) - Shantanu Dutt, Fran Hanchek:
REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 34-56 (1997) - M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf:
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 360-368 (1997) - Godi Fischer, James C. Daly, Conrad W. Recksiek, Kevin D. Friedland:
A programmable temperature monitoring device for tagging small fish: a prototype chip development. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 401-407 (1997) - Vadim Gutnik, Anantha P. Chandrakasan:
Embedded power supply for low-power DSP. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 425-435 (1997) - Qiuting Huang, Philipp Basedau:
Design considerations for high-frequency crystal oscillators digitally trimmable to sub-ppm accuracy. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 408-416 (1997) - Steve C.-Y. Huang, Wayne H. Wolf:
Unifiable scheduling and allocation for minimizing system cycle time. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 197-210 (1997) - Vijay K. Jain, Lei Lin:
Complex-argument universal nonlinear cell for rapid prototyping. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 15-27 (1997) - Yongjin Jeong, Wayne P. Burleson:
VLSI array algorithms and architectures for RSA modular multiplication. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 211-217 (1997) - Ahmed Amine Jerraya, Gert Goossens:
Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 57-58 (1997) - Kamal Kantawala, Dali L. Tao:
Design, analysis, and evaluation of concurrent checking sorting networks. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 338-343 (1997) - Zahava Koren, Israel Koren:
On the effect of floorplanning on the yield of large area integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 3-14 (1997) - Ram K. Krishnamurthy, L. Richard Carley:
Exploring the design space of mixed swing quadrail for low-power digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 388-400 (1997) - Yen-Tai Lai, Ping-Tsung Wang:
Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 186-196 (1997) - Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 123-135 (1997) - Rainer Leupers, Peter Marwedel:
Time-constrained code compaction for DSPs. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 112-122 (1997) - Yong Je Lim, Mani Soma:
Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 309-319 (1997) - Aaron Lipman, Woodward Yang:
VLSI hardware for example-based learning. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 320-328 (1997) - Jun Ma, Han-Bin Liang, R. A. Pryor, Sunny Cheng, M. H. Kaneshiro, C. S. Kyono, Ken Papworth:
Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 352-359 (1997)
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