• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 30 matches

• 1995
• 
  Vishwani D. Agrawal:
  Editorial. J. Electron. Test. 6(1): 5-6 (1995)
• 
  Vishwani D. Agrawal:
  Editorial. J. Electron. Test. 6(2): 147 (1995)
• 
  Vishwani D. Agrawal:
  Editorial. J. Electron. Test. 6(3): 263 (1995)
• 
  Maria J. Avedillo, José M. Quintana, José Luis Huertas:
  Constrained state assignment of easily testable FSMs. J. Electron. Test. 6(1): 133-138 (1995)
• 
  Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
  TIES: A testability increase expert system for VLSI design. J. Electron. Test. 6(2): 203-217 (1995)
• 
  Kevin Cattell, Shujian Zhang:
  Minimal cost one-dimensional linear hybrid cellular automata of degree through 500. J. Electron. Test. 6(2): 255-258 (1995)
• 
  Beyin Chen, Chung-Len Lee:
  Universal test set generation for CMOS circuits. J. Electron. Test. 6(3): 313-323 (1995)
• 
  Ilana David, Ran Ginosar, Michael Yoeli:
  Self-timed is self-checking. J. Electron. Test. 6(2): 219-228 (1995)
• 
  Geetani Edirisooriya, John P. Robinson:
  Authors' reply to comments on "Aliasing Properties of Circular MISRs". J. Electron. Test. 6(1): 141-142 (1995)
• 
  Kent L. Einspahr, Sharad C. Seth:
  A switch-level test generation system for synchronous and asynchronous circuits. J. Electron. Test. 6(1): 59-73 (1995)
• 
  Joan Figueras, Michel Renovell:
  Current testing in dynamic CMOS circuits. J. Electron. Test. 6(1): 127-131 (1995)
• 
  Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
  An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. 6(3): 277-294 (1995)
• 
  Oliver F. Haberl, Thomas Kropf:
  HIST: A hierarchical self test methodology for chips, boards, and systems. J. Electron. Test. 6(1): 85-106 (1995)
• 
  Kanji Hirabayashi:
  A parametric yield model. J. Electron. Test. 6(3): 331-332 (1995)
• 
  Dimitrios Kagaris, Spyros Tragoudas:
  Avoiding linear dependencies in LFSR test pattern generators. J. Electron. Test. 6(2): 229-241 (1995)
• 
  Wuudiann Ke, Premachandran R. Menon:
  Multifault and delay-fault testability of multilevel circuits. J. Electron. Test. 6(3): 333-336 (1995)
• 
  Konstantin Keutner, Erwin Trischler:
  Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits. J. Electron. Test. 6(1): 45-58 (1995)
• 
  D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier:
  A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes. J. Electron. Test. 6(1): 75-84 (1995)
• 
  William P. Marnane, Will R. Moore:
  Testing VLSI regular arrays. J. Electron. Test. 6(2): 153-177 (1995)
• 
  Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
  Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J. Electron. Test. 6(1): 7-22 (1995)
• 
  Fidel Muradali, Takao Nishida, Tsuguo Shimizu:
  A structure and technique for pseudorandom-based testing of sequential circuits. J. Electron. Test. 6(1): 107-115 (1995)
• 
  Michael Nicolaidis:
  Efficient UBIST implementation for microprocessor sequencing parts. J. Electron. Test. 6(3): 295-312 (1995)
• 
  Slawomir Pilarski:
  Comments on "Aliasing Properties of Circular MISRs". J. Electron. Test. 6(1): 139-140 (1995)
• 
  Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto:
  Testability of artificial neural networks: A behavioral approach. J. Electron. Test. 6(2): 179-190 (1995)
• 
  Manoj Sachdev:
  Reducing the CMOS RAM test complexity withI_DDQ and voltage testing. J. Electron. Test. 6(2): 191-202 (1995)
• 
  Manoj Sachdev:
  A realistic defect oriented testability methodology for analog circuits. J. Electron. Test. 6(3): 265-276 (1995)
• 
  Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle:
  Transient power supply current monitoring - A new test method for CMOS VLSI circuits. J. Electron. Test. 6(1): 23-43 (1995)
• 
  Soon Fatt Yoon:
  Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes. J. Electron. Test. 6(1): 117-125 (1995)
• 
  Shujian Zhang, Jon C. Muzio:
  Evaluating the safety of self-checking circuits. J. Electron. Test. 6(2): 243-253 (1995)
• 
  H. Zhou, Howard C. Card, Gregory E. Bridges:
  Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing. J. Electron. Test. 6(3): 325-330 (1995)