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Publication search results
found 31 matches
- 2011
- Shashank Bujimalla, Cheng-Kok Koh:
Synthesis of low power clock trees for handling power-supply variations. ISPD 2011: 37-44 - Tung-Chieh Chen:
Automated placement for custom digital designs. ISPD 2011: 89-90 - Xi Chen, Jiang Hu, Ning Xu:
Regularity-constrained floorplanning for multi-core processors. ISPD 2011: 99-106 - Chung-Kuan Cheng:
Placement and beyond in honor of Ernest S. Kuh. ISPD 2011: 5-8 - Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong:
More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166 - Fang Gong, Hao Yu, Lei He:
Stochastic analog circuit behavior modeling by point estimation method. ISPD 2011: 175-182 - Yi-Le Huang, Jiang Hu, Weiping Shi:
Lagrangian relaxation for gate implementation selection. ISPD 2011: 167-174 - Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen:
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. ISPD 2011: 115-122 - Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
3DICs for tera-scale computing: a case study. ISPD 2011: 77-78 - Johann Knechtel, Igor L. Markov, Jens Lienig:
Assembling 2D blocks into 3D chips. ISPD 2011: 81-88 - Ernest S. Kuh:
Professor Ernest Kuh's talk. ISPD 2011: 3-4 - Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang:
An enhanced global router with consideration of general layer directives. ISPD 2011: 53-60 - Dongjin Lee, Igor L. Markov:
Obstacle-aware clock-tree shaping during placement. ISPD 2011: 123-130 - Jianchao Lu, Xiaomi Mao, Baris Taskin:
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. ISPD 2011: 131-138 - Wojciech Maly:
Vertical slit transistor based integrated circuits (veSTICs): feasibility study. ISPD 2011: 147-148 - Malgorzata Marek-Sadowska:
On old and new routing problems. ISPD 2011: 13-20 - Tarun Mittal, Cheng-Kok Koh:
Cross link insertion for improving tolerance to variations in clock network synthesis. ISPD 2011: 29-36 - Robert Patti:
Advances in 3D integrated circuits. ISPD 2011: 79-80 - Massoud Pedram:
Robust design of power-efficient VLSI circuits. ISPD 2011: 1-2 - Vivek Singh:
Litho and design: moore close than ever. ISPD 2011: 149-150 - Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Grid-to-ports clock routing for high performance microprocessor designs. ISPD 2011: 21-28 - Ren-Song Tsay:
From academic ideas to practical physical design tools. ISPD 2011: 9-12 - Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - Alexander Volkov:
Impact of manufacturing on routing methodology at 32/22 nm. ISPD 2011: 139-140 - Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak:
Power-driven flip-flop merging and relocation. ISPD 2011: 107-114 - Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware length-matching bus routing. ISPD 2011: 61-68 - Kun Yuan, David Z. Pan:
E-beam lithography stencil planning and optimization with overlapped characters. ISPD 2011: 151-158 - Yanheng Zhang, Chris Chu:
RegularRoute: an efficient detailed router with regular routing patterns. ISPD 2011: 45-52 - Yang Zhao, Krishnendu Chakrabarty:
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips. ISPD 2011: 69-76
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