- Ali Jafari, Morteza Hosseini, Houman Homayoun, Tinoosh Mohsenin:
A Scalable and Low Power DCNN for Multimodal Data Classification. ReConFig 2018: 1-6 - Zheming Jin, Hal Finkel:
Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC Kernel. ReConFig 2018: 1-6 - Ievgen Kabin, Dan Kreiser, Zoya Dyka, Peter Langendörfer:
FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA. ReConFig 2018: 1-7 - Lester Kalms, Hassan Ibrahim, Diana Göhringer:
Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAK. ReConFig 2018: 1-6 - Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision. ReConFig 2018: 1-6 - William Kamp, Norbert Abel, Gianni Comoretto:
Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators. ReConFig 2018: 1-6 - Philipp S. Käsgen, Markus Weinhardt, Christian Hochberger:
A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications. ReConFig 2018: 1-4 - Safdar Mahmood, Pavel Shydlouski, Michael Hübner:
An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse Kinematics. ReConFig 2018: 1-6 - John McGlone, Paolo Palazzari
, J. B. Leclere:
Accelerating Key In-memory Database Functionality with FPGA Technology. ReConFig 2018: 1-8 - Paul Sathre, Ahmed E. Helal, Wu-chun Feng:
A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and Transformation. ReConFig 2018: 1-8 - Arpit Soni, Yoon Kah Leow, Ali Akoglu
:
Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures. ReConFig 2018: 1-8 - Franz-Josef Streit
, Martín Letras
, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher
, Jürgen Teich:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig 2018: 1-8 - Weiyi Sun, Hanqing Zeng, Yi-Hua Edward Yang, Viktor K. Prasanna:
Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGA. ReConFig 2018: 1-8 - Gustavo Sutter, Mario Ruiz
, Sergio López-Buedo, Gustavo Alonso:
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig 2018: 1-6 - Takashi Takemoto, Normann Mertig
, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki
, Masanao Yamaoka:
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig 2018: 1-8 - Michael Tempelmeier
, Georg Sigl, Jens-Peter Kaps
:
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. ReConFig 2018: 1-6 - Hsin-Yu Ting, Ardalan Amiri Sani, Eli Bozorgzadeh:
System Services for Reconfigurable Hardware Acceleration in Mobile Devices. ReConFig 2018: 1-6 - Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
:
LaKe: The Power of In-Network Computing. ReConFig 2018: 1-8 - Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas
, Vianney Lapotre
, Guy Gogniat
:
A small and adaptive coprocessor for information flow tracking in ARM SoCs. ReConFig 2018: 1-8 - Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao:
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig 2018: 1-8 - Rafael Zamacola, Alberto García-Martínez
, Javier Mora
, Andrés Otero
, Eduardo de la Torre:
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig 2018: 1-8 - Daniel Ziener
, Jutta Pirkl, Jürgen Teich:
Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig 2018: 1-7 - David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt:
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018. IEEE 2018, ISBN 978-1-7281-1968-7 [contents] - 2017
- Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. ReConFig 2017: 1-6 - Ian J. Barge, Cristinel Ababei:
H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip. ReConFig 2017: 1-6 - Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph
, Thilo Pionteck
:
Continuous live-tracing as debugging approach on FPGAs. ReConFig 2017: 1-8 - Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow:
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. ReConFig 2017: 1-6 - Anthony Brandon, Michael Trimarchi:
Trusted display and input using screen overlays. ReConFig 2017: 1-6 - Pedro Bruel, Alfredo Goldman
, Sai Rahul Chalamalasetti, Dejan S. Milojicic
:
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. ReConFig 2017: 1-6 - Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. ReConFig 2017: 1-6