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ORCIDChristopher Blochwitz
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2020 – today
- 2022
[c15]Christopher Blochwitz, Philipp Grothe, Sven Dreier, Waiel Aljnabi, Rainer Buchty, Mladen Berekovic
:
RemEduLa - Remote Education Laboratory for FPGA Design Technology. ISCAS 2022: 1773-1777- 2021
- [c14]Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck:
StreamGrid - An AXI-Stream-Compliant Overlay Architecture. ARC 2021: 156-170 - [c13]Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic:
A comparative survey of open-source application-class RISC-V processor implementations. CF 2021: 12-20 - 2020
- [j5]Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe:
Hardware-aided update acceleration in a hybrid Semantic Web database system. J. Supercomput. 76(10): 7961-7984 (2020)
2010 – 2019
- 2018
- [c12]Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck:
Hardware-Accelerated Index Construction for Semantic Web. FPT 2018: 278-281 - 2017
- [j4]Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems 48: 36-47 (2017) - [c11]Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck:
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. ARCS 2017: 47-58 - [c10]Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck:
Continuous live-tracing as debugging approach on FPGAs. ReConFig 2017: 1-8 - [c9]Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck:
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig 2017: 1-8 - 2016
- [j3]Sven Groppe, Dennis Heinrich, Christopher Blochwitz, Thilo Pionteck:
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders. Open J. Big Data 2(1): 11-25 (2016) - [j2]Stefan Werner, Dennis Heinrich, Sven Groppe, Christopher Blochwitz, Thilo Pionteck:
Runtime Adaptive Hybrid Query Engine based on FPGAs. Open J. Databases 3(1): 21-41 (2016) - [c8]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck:
Adaptive allocation of default router paths in Network-on-Chips for latency reduction. HPCS 2016: 140-147 - [c7]Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck:
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig 2016: 1-7 - [c6]Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC 2016: 1-8 - 2015
- [j1]Sven Groppe, Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck:
PatTrieSort - External String Sorting based on Patricia Tries. Open J. Databases 2(1): 36-50 (2015) - [c5]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz:
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS 2015: 1-4 - [c4]Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck:
An architectural template for composing application specific datapaths at runtime. ReConFig 2015: 1-6 - [c3]Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe:
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. ReConFig 2015: 1-7 - [c2]Dennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe:
Hybrid FPGA approach for a B+ tree in a Semantic Web database system. ReCoSoC 2015: 1-8 - [c1]Stefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe, Rico Backasch, Christopher Blochwitz, Thilo Pionteck:
Automated composition and execution of hardware-accelerated operator graphs. ReCoSoC 2015: 1-8
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