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ORCIDZhongyuan Zhao 0004
Person information
- affiliation: Cornell University, School of Electrical and Computer Engineering, Ithaca, NY, USA
- affiliation: Shanghai Jiao Tong University, Department of Micro/Nano Electronics, China
Other persons with the same name
- Zhongyuan Zhao — disambiguation page
- Zhongyuan Zhao 0001
![[0000-0002-8218-7723]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-8218-7723")
— Beijing University of Posts and Telecommunications, Institute of Information and Communication, China (and 1 more) - Zhongyuan Zhao 0002 — Rice University, Department of Electrical and Computer Engineering, Houston, TX, USA (and 3 more)
- Zhongyuan Zhao 0003 — Chongqing University, College of Automation, Key Laboratory of Dependable Service Computing in Cyber Physical Society, China
- Zhongyuan Zhao 0005 — Zhoukou Normal University, School of Science and Technology, Henan, China
- Zhongyuan Zhao 0006 — East China Normal University, School of Communication and Electronic Engineering, Shanghai, China
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2020 – today
- 2024
[i1]Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang:
UniSparse: An Intermediate Language for General Sparse Format Customization. CoRR abs/2403.05802 (2024)- 2022
- [j2]Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten:
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1620-1635 (2022) - 2021
- [c8]Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng:
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. DATE 2021: 124-129 - 2020
- [j1]Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao:
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 31(9): 2201-2219 (2020)
2010 – 2019
- 2019
- [c7]Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna:
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. ISPASS 2019: 282-292 - 2018
- [c6]Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao:
Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE 2018: 1087-1092 - [c5]Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao:
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig 2018: 1-8 - 2017
- [c4]Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li:
A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE 2017: 1348-1353 - 2016
- [c3]Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao:
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT 2016: 233-236 - 2015
- [c2]Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao:
Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. PRDC 2015: 325-326 - [c1]Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao:
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig 2015: 1-8
Coauthor Index
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