- Jason Doege, Alfred L. Crouch:
The Advantages of Limiting P1687 to a Restricted Subset. ITC 2008: 1-8 - Dave F. Dubberke, James J. Grealish, Bill Van Dick:
Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application. ITC 2008: 1-9 - Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji:
DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. ITC 2008: 1-10 - Heiko Ehrenberg:
IEEE P1581 drastically simplifies connectivity test for memory devices. ITC 2008: 1 - Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi:
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. ITC 2008: 1-10 - Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem:
On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC 2008: 1-7 - William Fritzsche, Asim E. Haque:
Low cost testing of multi-GBit device pins with ATE assisted loopback instrument. ITC 2008: 1-8 - Anne Gattiker:
Unraveling Variability for Process/Product Improvement. ITC 2008: 1-9 - Jeroen Geuzebroek, Bart Vermeulen:
Integration of Hardware Assertions in Systems-on-Chip. ITC 2008: 1-10 - Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test Access Mechanism for Multiple Identical Cores. ITC 2008: 1-10 - Olivier Ginez, Jean-Michel Portal, Hassen Aziza:
A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. ITC 2008: 1-10 - Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng:
Detection and Diagnosis of Static Scan Cell Internal Defect. ITC 2008: 1-10 - Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng:
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10 - Steve Hird, Reggie Weng:
Finding Power/Ground Defects on Connectors - Case Study. ITC 2008: 1-4 - I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9 - Lin Huang, Qiang Xu:
Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy? ITC 2008: 1 - Hiroaki Inoue, Yanjing Li, Subhasish Mitra:
VAST: Virtualization-Assisted Concurrent Autonomous Self-Test. ITC 2008: 1-10 - Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas:
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. ITC 2008: 1-10 - Wei Jiang, Vishwani D. Agrawal:
Built-in Self-Calibration of On-chip DAC and ADC. ITC 2008: 1-10 - Le Jin:
Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter Estimation. ITC 2008: 1-8 - Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris:
On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. ITC 2008: 1-10 - Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka:
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. ITC 2008: 1-7 - David C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid:
An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. ITC 2008: 1-9 - Ajay Khoche, Phil Burlison, John Rowe, Glenn Plowman:
A Tutorial on STDF Fail Datalog Standard. ITC 2008: 1-10 - Gyu-Yeol Kim, Eon-Jo Byunb, Ki-Sang Kang, Young-Hyun Jun, Bai-Sun Kong:
Wafer-Level Characterization of Probecards using NAC Probing. ITC 2008: 1-9 - Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC 2008: 1-10 - Satoshi Komatsu:
VLSI Test Exercise Courses for Students in EE Department. ITC 2008: 1 - Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer:
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation. ITC 2008: 1-7 - Jaekwang Lee, Edward J. McCluskey:
Failing Frequency Signature Analysis. ITC 2008: 1-8