- Patrick Sittel, Nicolai Fiege
, Martin Kumm, Peter Zipf
:
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig 2019: 1-8 - Wesley Stirk, Jeffrey Goeders:
Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. ReConFig 2019: 1-5 - Beck Strohmer
, Anders Bøgild
, Anders Stengaard Sørensen
, Leon Bonde Larsen
:
ROS-Enabled Hardware Framework for Experimental Robotics. ReConFig 2019: 1-2 - Adrian Tatulian, Soheil Salehi, Ronald F. DeMara:
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing. ReConFig 2019: 1-8 - Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn
, Andreas Dengel:
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction. ReConFig 2019: 1-8 - Corbin Thurlow, Hayden Rowberry, Michael J. Wirthlin:
TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs. ReConFig 2019: 1-8 - Burak Unal
, Md Sahil Hassan
, Joshua Mack
, Nirmal Kumbhare, Ali Akoglu
:
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes. ReConFig 2019: 1-8 - Cristian Urlea, Wim Vanderbauwhede, Syed Waqar Nabi
:
Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations. ReConFig 2019: 1-2 - Nils Voss, Stephen Girdlestone, Tobias Becker
, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev
:
Low Area Overhead Custom Buffering for FFT. ReConFig 2019: 1-8 - David Wilson, Greg Stitt:
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development. ReConFig 2019: 1-8 - Andrew E. Wilson, Michael J. Wirthlin:
Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs. ReConFig 2019: 1-7 - Tolga Yalçin
, Elif Bilge Kavun:
Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices. ReConFig 2019: 1-6 - David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner:
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019. IEEE 2019, ISBN 978-1-7281-1957-1 [contents] - 2018
- Ahmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet:
An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs. ReConFig 2018: 1-6 - Gökhan Akgün, Habib ul Hasan Khan, Mahmoud Ahmed Elshimy, Diana Göhringer:
Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loop. ReConFig 2018: 1-8 - Joe Avey, Phillip H. Jones, Joseph Zambreno:
An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig 2018: 1-8 - Matthew Cauwels, Joseph Zambreno, Phillip H. Jones:
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig 2018: 1-8 - Sourya Dey
, Diandian Chen, Zongyang Li, Souvik Kundu
, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel:
A Highly Parallel FPGA Implementation of Sparse Neural Network Training. ReConFig 2018: 1-4 - Zoya Dyka, Dan Kreiser, Ievgen Kabin, Peter Langendörfer:
Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCA. ReConFig 2018: 1-6 - Alan Ehret, Mihailo Isakov, Michel A. Kinsy:
Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration. ReConFig 2018: 1-6 - Vladimir Estivill-Castro
, René Hexel
, Morgan McColl
:
High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAs. ReConFig 2018: 1-8 - Ahmed Ferozpuri, Kris Gaj:
High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme. ReConFig 2018: 1-8 - Paulina Fusiara, Gijs Schoonderbeek, Johan Pragt, Leon Hiemstra, Sjouke Kuindersma, Menno Schuil, Grant Hampson:
Design and Fabrication of Full Board Direct Liquid Cooling Heat Sink for Densely Packed FPGA Processing Boards. ReConFig 2018: 1-8 - William L. Harrison, Gerard Allwein:
Language Abstractions for Hardware-based Control-Flow Integrity Monitoring. ReConFig 2018: 1-6 - Mohamed W. Hassan, Ahmed E. Helal, Peter M. Athanas, Wu-Chun Feng, Yasser Y. Hanafy:
Exploring FPGA-specific Optimizations for Irregular OpenCL Applications. ReConFig 2018: 1-8 - Kris Heid, Christian Hochberger:
AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCs. ReConFig 2018: 1-7 - Kalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan:
Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs. ReConFig 2018: 1-8 - Dillon Huff, Pat Hanrahan:
Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures. ReConFig 2018: 1-6 - Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig 2018: 1-6