- 2015
- Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh:
Methodology for optimizing ESD protection for high speed LVDS based I/Os. VDAT 2015: 1-5 - Kshitij Agrawal, Shubhajit Roy Chowdhury:
Real time multisensor Laplacian fusion on FPGA. VDAT 2015: 1-4 - Arindam Banerjee, Debesh Kumar Das:
Squarer design with reduced area and delay. VDAT 2015: 1-6 - Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das:
Partitioning-based test time reduction for core-based 3DICs. VDAT 2015: 1-5 - Ansuman Banerjee, Arijit Mondal, Arnab Sarkar, Santosh Biswas:
Real-time embedded systems analysis - From theory to practice. VDAT 2015: 1-2 - Binal B. Baraiya, Hiren K. Mewada, Amish B. Shah:
FPGA based disk controller and photon counter of optical polarimeter. VDAT 2015: 1-6 - Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad:
On-chip CMOS temperature sensor with current calibrated accuracy of -1.1°C to +1.4°C (3σ) from -20°C to 150°C. VDAT 2015: 1-5 - Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad:
High speed self biased current sense amplifier for low power CMOS SRAM's. VDAT 2015: 1-5 - Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
GA based diagnostic test pattern generation for transition faults. VDAT 2015: 1-6 - Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. VDAT 2015: 1-6 - Sarit Chakraborty, Chandan Das, Susanta Chakraborty, Parthasarathi Dasgupta:
A novel two phase heuristic routing technique in digital microfluidic biochip. VDAT 2015: 1-6 - Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Power aware cache miss reduction by energy efficient victim retention. VDAT 2015: 1-6 - Bidesh Chakraborty, Bhanu Pratap Singh, M. Chinnapureddy, Mamata Dalui, Biplab K. Sikdar:
Design of coherence verification unit for heterogeneous CMPs. VDAT 2015: 1-6 - Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur:
Designing efficient combinational compression architecture for testing industrial circuits. VDAT 2015: 1-6 - Santanu Chattopadhyay:
Power- and thermal-aware testing of VLSI circuits and systems. VDAT 2015: 1 - Rekha Chaudhary, Amit Sharma, Soumendu Sinha, Jitendra Yadav, Rishi Sharma, Ravindra Mukhiya, Vinod K. Khanna:
Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET. VDAT 2015: 1-4 - Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand:
Timing model for two stage buffer and its application in ECSM characterization. VDAT 2015: 1-6 - Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan:
Thermal aware AND-OR-XOR network synthesis. VDAT 2015: 1-6 - Sandeep D'Souza, Soumya J., Santanu Chattopadhyay:
A constructive heuristic for application mapping onto an express channel based Network-on-Chip. VDAT 2015: 1-6 - Anand D. Darji, Raviraj P. Makwana:
High-performance multiplierless DCT architecture for HEVC. VDAT 2015: 1-5 - Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar:
Parallel two step random walk algorithm to analyze VLSI power grid networks. VDAT 2015: 1-2 - Debarati Dey, Pradipta Roy, Debashis De:
Molecular modeling of Nano bio p-i-n FET. VDAT 2015: 1-6 - Debasis Dhal, Piyali Datta, Arpan Chakrabarty, Sudipta Roy, Rajat Kumar Pal:
An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance. VDAT 2015: 1-6 - Vaishali H. Dhare, Usha Mehta:
Defect characterization and testing of QCA devices and circuits: A survey. VDAT 2015: 1-2 - Arpita Dutta, Santanu Chattopadhyay:
Particle swarm optimization approach for low temperature BIST. VDAT 2015: 1-6 - Pradyumna Galgali, Surendra S. Rathod:
Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay. VDAT 2015: 1-5 - Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Manoj Kumar, Niyati Gupta, Ashish Sharma:
Network-on-chip: Current issues and challenges. VDAT 2015: 1-3 - Prokash Ghosh, Sandip Ghosh, Pritpal Singh, Saurabh Mishra:
Case study: Re-visiting SoC verification challenges and best practices. VDAT 2015: 1-9 - M. R. Gowthami, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli:
Modified low power scan based technique. VDAT 2015: 1-5 - Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks. VDAT 2015: 1-6