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Surendra S. Rathod
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2020 – today
- 2024
- [j9]Payal Shah
, Satvik Sawant, Reena Sonkusare, Surendra S. Rathod:
Modelling and design of asynchronous receptive circuit for cone pathways. Integr. 94: 102112 (2024) - 2020
- [c4]Sayli Shinde, Manisha Bansode, Pramod P. Bhavarthe, Surendra S. Rathod
:
Suppression of SSN in High-Speed Circuits using 1-D EBG structure. ICCCNT 2020: 1-4
2010 – 2019
- 2019
- [j8]Reena Sonkusare, Omkar Joshi, Surendra S. Rathod
:
SOI FinFET based instrumentation amplifier for biomedical applications. Microelectron. J. 91: 1-10 (2019) - 2017
- [c3]Sushma Srivastava, Surendra S. Rathod
:
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology. VDAT 2017: 136-143 - 2015
- [c2]Jinalkumar Doshi, Pratiksha Patil, Zalak Dave, Ganesh Gore, Jonathan Joshi, Reena Sonkusare, Surendra S. Rathod
:
Implementing a cloud based Xilinx ISE FPGA design platform for integrated remote labs. ICACCI 2015: 533-537 - [c1]Pradyumna Galgali, Surendra S. Rathod
:
Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay. VDAT 2015: 1-5 - 2012
- [j7]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. 6(4): 218-226 (2012) - [j6]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. 21(4) (2012) - 2011
- [j5]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. 5(1): 52-58 (2011) - [j4]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. 42(1): 165-172 (2011) - [j3]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. 51(4): 773-780 (2011) - 2010
- [j2]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. 6(4): 533-544 (2010) - [j1]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. 50(8): 1181-1188 (2010)
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