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ORCIDKang Wook Lee 0002
Person information
- affiliation: Tohoku University, Sendai, Japan
Other persons with the same name
- Kangwook Lee 0001
![[0000-0002-3360-9678]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-3360-9678")
(aka: Kang Wook Lee 0001) — University of Wisconsin Madison, WI, USA (and 2 more) - Kang-Wook Lee 0003 (aka: Kangwook Lee 0003) — Thomas J. Watson Research Center, IBM Research Division, Yorktown Heights, NY
- Kangwook Lee 0004 — Samsung Research
- Kangwook Lee 0005 — Amkor Technology Korea, Inc, Incheon, South Korea
- Kangwook Lee 0006 — Korea Advanced Institute of Science and Technology, Daejeon, South Korea
- Kangwook Lee 0007 — Georgia Institute of Technology, School of Chemical Engineering, Atlanta, GA, USA
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Journal Articles
- 2016
[j3]Takafumi Fukushima, Hideto Hashiguchi, Hiroshi Yonekura, Hisashi Kino, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. Micromachines 7(10): 184 (2016)- 2011
- [j2]Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines 2(1): 49-68 (2011) - 1998
- [j1]Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani:
Future system-on-silicon LSI chips. IEEE Micro 18(4): 17-22 (1998)
Conference and Workshop Papers
- 2016
- [c28]Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC 2016: 1-4 - [c27]Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi:
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. 3DIC 2016: 1-5 - 2015
- [c26]Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. 3DIC 2015: TS5.2.1-TS5.2.5 - [c25]Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi:
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC 2015: TS7.4.1-TS7.4.4 - [c24]Kang Wook Lee, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. IRPS 2015: 4 - 2014
- [c23]Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi:
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 3DIC 2014: 1-4 - 2013
- [c22]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Mitsumasa Koyanagi:
Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC 2013: 1-4 - [c21]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Ho-Young Son, M.-S. Suh, K.-Y. Byun, N.-S. Kim, Kang Wook Lee, Mitsumasa Koyanagi:
3D memory chip stacking by multi-layer self-assembly technology. 3DIC 2013: 1-4 - [c20]Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka:
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 3DIC 2013: 1-5 - [c19]Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. 3DIC 2013: 1-4 - [c18]Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC 2013: 1-4 - [c17]Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Yuji Sutou, H. Wang, J. Koike:
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 3DIC 2013: 1-4 - 2011
- [c16]Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Temporary bonding strength control for self-assembly-based 3D integration. 3DIC 2011: 1-4 - [c15]Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Chip-level TSV integration for rapid prototyping of 3D system LSIs. 3DIC 2011: 1-4 - [c14]Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi:
A very low area ADC for 3-D stacked CMOS image processing system. 3DIC 2011: 1-4 - [c13]Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Yuki Ohara, Tetsu Tanaka, Mitsumasa Koyanagi:
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. 3DIC 2011: 1-4 - [c12]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. 3DIC 2011: 1-4 - [c11]Yuki Ohara, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. 3DIC 2011: 1-4 - 2010
- [c10]Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 - [c9]Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, Hiroaki Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi:
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. 3DIC 2010: 1-4 - [c8]Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC 2010: 1-5 - [c7]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 3DIC 2010: 1-4 - 2009
- [c6]Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisashi Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC 2009: 1-5 - [c5]Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
3D integration technology for 3D stacked retinal chip. 3DIC 2009: 1-4 - [c4]Kouji Kiyoyama, Yuki Ohara, Kang Wook Lee, Y. Yang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
A parallel ADC for high-speed CMOS image processing system with 3D structure. 3DIC 2009: 1-4 - [c3]Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Heterogeneous integration technology for MEMS-LSI multi-chip module. 3DIC 2009: 1-6 - [c2]Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6 - 2000
- [c1]Hiroyuki Kurino, Masaki Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi:
Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. NIPS 2000: 720-726
Coauthor Index
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