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ORCIDC. Y. Roger Chen
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- affiliation: Syracuse University, Syracuse, NY, USA
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2020 – today
- 2022
[j26]Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu:
CWcollab: Presenting multimedia with web-based context-aware collaboration. Entertain. Comput. 43: 100511 (2022)- [i1]Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu:
CWcollab: A Context-Aware Web-Based Collaborative Multimedia System. CoRR abs/2204.06134 (2022) - 2021
- [c46]Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu:
CWcollab: A Context-Aware Web-Based Collaborative Multimedia System. ICC 2021: 1-6
2010 – 2019
- 2016
- [j25]Jae Woong Chun
, Chien-Yi Roger Chen:
Leakage power reduction using the body bias and pin reordering technique. IEICE Electron. Express 13(3): 20151052 (2016) - [j24]Jae Woong Chun, C. Y. Roger Chen:
Transistor and pin reordering for leakage reduction in CMOS circuits. Microelectron. J. 53: 25-34 (2016) - 2015
- [c45]Jiani Xie, C. Y. Roger Chen:
Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model. ACM Great Lakes Symposium on VLSI 2015: 361-366 - 2012
- [c44]B. S. Deepaksubramanyan, C. Y. Roger Chen, Adrian Nunez:
A tool to generate models based on behavioral IBIS models. MWSCAS 2012: 234-237
2000 – 2009
- 2008
- [c43]Veerapaneni Nagbhushan, C. Y. Roger Chen:
Modeling and reduction of complex timing constraints in high performance digital circuits. ICCD 2008: 544-550 - 2007
- [c42]Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
A technique for selecting CMOS transistor orders. ICCD 2007: 438-443 - [c41]Veerapaneni Nagbhushan, C. Y. Roger Chen:
Algorithms to simplify multi-clock/edge timing constraints. ICCD 2007: 444-449 - [c40]Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
An efficient gate delay model for VLSI design. ICCD 2007: 450-455 - 2003
- [c39]Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
A novel ultra-fast heuristic for VLSI CAD steiner trees. ACM Great Lakes Symposium on VLSI 2003: 192-197 - [c38]Bill Halpin, Naresh Sehgal, C. Y. Roger Chen:
Detailed Placement with Net Length Constraints. IWSOC 2003: 22-27 - 2001
- [c37]Bill Halpin, C. Y. Roger Chen, Naresh Sehgal:
Timing Driven Placement using Physical Net Constraints. DAC 2001: 780-783 - 2000
- [j23]Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen:
Partitionable multistage interconnection networks. Part 2: Task migration schemes. Telecommun. Syst. 13(1): 45-67 (2000) - [j22]Dikran S. Meliksetian, Frank Feng-Kuo Yu, C. Y. Roger Chen:
Methodologies for Designing Video Servers. IEEE Trans. Multim. 2(1): 62-69 (2000) - [c36]Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
A novel technique for sea of gates global routing. ACM Great Lakes Symposium on VLSI 2000: 71-74 - [c35]Bill Halpin, C. Y. Roger Chen, Naresh Sehgal:
A sensitivity based placer for standard cells. ACM Great Lakes Symposium on VLSI 2000: 193-196
1990 – 1999
- 1999
- [j21]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology. Discret. Appl. Math. 90(1-3): 89-114 (1999) - 1998
- [j20]Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen:
Partitionable multistage interconnection networks. Part 1: Dynamic subcube compaction. Telecommun. Syst. 10(1): 79-106 (1998) - [c34]Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. VLSI Design 1998: 53-58 - 1997
- [c33]Tacettin Kiprulu, Dikran S. Meliksetian, C. Y. Roger Chen:
Smoothing Algorithms for the Delivery of Compressed Video. ICC (3) 1997: 1330-1334 - 1996
- [c32]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Transistor Chaining in CMOS Leaf Cells of Planar Topology. Great Lakes Symposium on VLSI 1996: 194-199 - 1995
- [j19]Arif Ghafoor, C. Y. Roger Chen:
Special Issue on Multimedia Processing and Technology. J. Parallel Distributed Comput. 30(2): 107-110 (1995) - [j18]C. Y. Roger Chen, Dikran S. Meliksetian, M. C. Chang, L. J. Liu:
Design of a Multimedia Object-Oriented DBMS. Multim. Syst. 3(5-6): 217-227 (1995) - [j17]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Dual Eulerian Properties of Plane Multigraphs. SIAM J. Discret. Math. 8(1): 33-50 (1995) - [j16]C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson:
A preprocessor for improving channel routing hierarchical pin permutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 896-903 (1995) - [j15]C. Y. Roger Chen, Cliff Yungchin Hou:
A pin permutation algorithm for improving over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1030-1037 (1995) - [j14]Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson:
LILA: layout generation for iterative logic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1359-1369 (1995) - [j13]C. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad:
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. IEEE/ACM Trans. Netw. 3(6): 708-715 (1995) - [j12]C. Y. Roger Chen, Georges A. Makhoul, Dikran S. Meliksetian:
A queueing analysis of the performance of DQDB. IEEE/ACM Trans. Netw. 3(6): 872-881 (1995) - [c31]Calvin J. A. Hsia, C. Y. Roger Chen:
Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs. ISCAS 1995: 1074-1077 - 1994
- [j11]Kingsley C. Nwosu, C. Y. Roger Chen, P. Bruce Berra:
Multimedia Object Modeling and Storage Allocation Strategies. J. Intell. Inf. Syst. 3(3/4): 357-398 (1994) - [j10]C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh:
Optimal algorithms for bubble sort based non-Manhattan channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 603-609 (1994) - [j9]Shuo-Hsien Hsiao, C. Y. Roger Chen:
Performance analysis of single-buffered multistage interconnection networks. IEEE Trans. Commun. 42(9): 2722-2729 (1994) - [j8]James V. Luciani, C. Y. Roger Chen:
An analytical model for partially blocking finite-buffered switching networks. IEEE/ACM Trans. Netw. 2(5): 533-540 (1994) - [c30]Mohammed Aloqeely, C. Y. Roger Chen:
Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms. DAC 1994: 155-160 - [c29]C. Y. Roger Chen, Mohammed Aloqeely:
A new technique for exploiting regularity in data path synthesis. EURO-DAC 1994: 394-399 - [c28]Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen:
Synthesis of Application-Specific Multiprocessor Systems. EDAC-ETC-EUROASIC 1994: 671 - [c27]Naresh Sehgal, C. Y. Roger Chen, John M. Acken:
A gridless multi-layer area router. Great Lakes Symposium on VLSI 1994: 158-161 - [c26]Naresh Sehgal, C. Y. Roger Chen, John M. Acken:
An object-oriented cell library manager. ICCAD 1994: 750-753 - [c25]Qinghong Wu, C. Y. Roger Chen, John M. Acken:
Efficent Boolean Matching Algorithm for Cell Libraries. ICCD 1994: 36-39 - [c24]Naresh Kumar Seghal, C. Y. Roger Chen, John M. Acken:
A High Performance General Purpose Multi-Point Signal Router. ISCAS 1994: 475-478 - [c23]Abdulaziz S. Mazyad, C. Y. Roger Chen:
Performance Evaluation of HIPPI Interconnection System Using a Camp-On Strategy. LCN 1994: 20-29 - 1993
- [j7]Dikran S. Meliksetian, C. Y. Roger Chen:
Optimal Routing Algorithm and the Diameter of the Cube-Connected Cycles. IEEE Trans. Parallel Distributed Syst. 4(10): 1172-1178 (1993) - [c22]C. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra:
Multimedia object modelling and storage allocation strategies for heterogeneous parallel access storage devices in real time multimedia computing systems. COMPSAC 1993: 216-223 - [c21]Bradley S. Carlson, C. Y. Roger Chen:
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. DAC 1993: 361-366 - [c20]C. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra:
Modeling and Storage Allocation Strategies for Homogeneous Parallel Access Storage Devices in Real Time Multimedia Information Processing. ICCI 1993: 565-569 - [c19]Shuo-Hsien Hsiao, C. Y. Roger Chen:
A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection Networks. IPPS 1993: 773-777 - [c18]Dikran S. Meliksetian, C. Y. Roger Chen:
A Markov-Modulated Bernoulli Process Approximation for the Analysis of Banyan Networks. SIGMETRICS 1993: 183-194 - [e1]C. Y. Roger Chen, P. Bruce Berra:
Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume I: Architecture. CRC Press 1993, ISBN 0-8493-8984-4 [contents] - 1992
- [j6]Uminder Singh, C. Y. Roger Chen:
From logic to symbolic layout for gate matrix. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 216-227 (1992) - [j5]Shuo-Hsien Hsiao, C. Y. Roger Chen:
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. IEEE Trans. Parallel Distributed Syst. 3(5): 632-640 (1992) - [c17]Cliff Yungchin Hou, C. Y. Roger Chen:
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing. DAC 1992: 594-599 - [c16]Imtiaz Ahmad, C. Y. Roger Chen:
A heuristic for data path synthesis using multiport memories. Great Lakes Symposium on VLSI 1992: 44-51 - [c15]P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Thomas D. C. Little:
Issues in Networking and Data Management of Distributed Multimedia Systems. HPDC 1992: 4-15 - [c14]Muhammad F. Mudawwar, C. Y. Roger Chen:
The Signal Flow Model: A novel Data Driven Approach to Parallel Processing. ICPP (1) 1992: 196-200 - [c13]Dikran S. Meliksetian, C. Y. Roger Chen:
Performance Analysis of Communications in Static Interconnection Networks. SIGMETRICS 1992: 249-250 - 1991
- [j4]Thomas D. C. Little, C. Y. Roger Chen, C. S. Chang, P. Bruce Berra:
Multimedia Synchronization. IEEE Data Eng. Bull. 14(3): 26-35 (1991) - [j3]C. Y. Roger Chen, Michael Z. Moricz:
A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 685-697 (1991) - [j2]Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh:
Optimal cell generation for dual independent layout styles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 770-782 (1991) - [c12]C. Y. Roger Chen, Michael Z. Moricz:
Datapath Scheduling for Two-Level Pipelining. DAC 1991: 603-606 - [c11]Imtiaz Ahmad, C. Y. Roger Chen:
Post-Processor for Data Path Synthesis Using Multiport Memories. ICCAD 1991: 276-279 - [c10]Cliff Yungchin Hou, C. Y. Roger Chen:
A Hierarchical Methodology to Improve Channel Routing by Pin Permutation. ICCAD 1991: 440-443 - [c9]Shuo-Hsien Hsiao, C. Y. Roger Chen:
Performance analysis of single-buffered multistage interconnection networks. SPDP 1991: 864-867 - 1990
- [j1]P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Chin Chung Lin, Thomas D. C. Little, Donghoon Shin:
Architecture for distributed multimedia database systems. Comput. Commun. 13(4): 217-231 (1990) - [c8]Uminder Singh, C. Y. Roger Chen:
A Transistor Reordering Technique for Gate Matrix Layout. DAC 1990: 462-467 - [c7]C. Y. Roger Chen, Yeh-Ching Chung:
Embedding Networks with Ring Connections in Hypercube Machines. ICPP (3) 1990: 327-334 - [c6]Calvin J. A. Hsia, C. Y. Roger Chen:
Permutation Capability of Multistage Interconnection Networks. ICPP (1) 1990: 338-346 - [c5]Dikran S. Meliksetian, C. Y. Roger Chen:
Communication Aspects of the Cube Connected Cycles. ICPP (1) 1990: 579-580
1980 – 1989
- 1989
- [c4]Calvin J. A. Hsia, C. Y. Roger Chen:
On a class of (2n-1)-stage rearrangeable interconnection networks. ICCD 1989: 452-455 - 1988
- [c3]C. Y. Roger Chen, Cliff Yungchin Hou:
A new algorithm for CMOS gate matrix layout. ICCAD 1988: 138-141 - [c2]C. Y. Roger Chen, Cliff Yungchin Hou:
A new layout optimization methodology for CMOS complex gates. ICCAD 1988: 368-371 - [c1]C. Y. Roger Chen:
TOBOL - a new methodology for the top-to-bottom level hardware description in VLSI design-automation systems. ICCL 1988: 404-411
Coauthor Index
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