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Bradley S. Carlson
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2000 – 2009
- 2001
- [c12]Bradley S. Carlson:
Principles vs. Practices in Undergraduate Microelectronic Systems Education. MSE 2001: 22-23 - 2000
- [c11]Hung-Jung Chen, Bradley S. Carlson:
Power estimation for a submicron CMOS inverter driving a CRC interconnect load. ACM Great Lakes Symposium on VLSI 2000: 162-166
1990 – 1999
- 1999
- [j9]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology. Discret. Appl. Math. 90(1-3): 89-114 (1999) - 1998
- [c10]Yen-Fu Liu, Nai-Wei Lo, Murali Subbarao, Bradley S. Carlson:
Parallel implementation of a unified approach to image focus and defocus analysis on the Parallel Virtual Machine. Visual Information Processing 1998: 100-111 - 1997
- [j8]Nai-Wei Lo, Bradley S. Carlson, D. L. Tao:
Fault Tolerant Algorithms for Broadcasting on the Star Graph Network. IEEE Trans. Computers 46(12): 1357-1362 (1997) - [j7]Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson:
Parallel logic simulation on a network of workstations using parallel virtual machine. ACM Trans. Design Autom. Electr. Syst. 2(2): 123-134 (1997) - [c9]Zhang Zhu, Bradley S. Carlson:
Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family. ICCD 1997: 732-737 - [c8]Bradley S. Carlson:
A VLSI circuit design course for practitioners and researchers. MSE 1997: 9-10 - 1996
- [j6]Yuan Hu, Bradley S. Carlson:
A Unified Algorithm for the Estimation and Scheduling of Data Flow Graphs. J. Circuits Syst. Comput. 6(3): 287-318 (1996) - [c7]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Transistor Chaining in CMOS Leaf Cells of Planar Topology. Great Lakes Symposium on VLSI 1996: 194-199 - [c6]Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson:
Parallel logic simulation on a network of workstations using PVM. SPDP 1996: 2-9 - 1995
- [j5]Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Dual Eulerian Properties of Plane Multigraphs. SIAM J. Discret. Math. 8(1): 33-50 (1995) - [j4]C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson:
A preprocessor for improving channel routing hierarchical pin permutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 896-903 (1995) - [j3]Bradley S. Carlson, Suh-Juch Lee:
Delay optimization of digital CMOS VLSI circuits by transistor reordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1183-1192 (1995) - [j2]Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson:
LILA: layout generation for iterative logic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1359-1369 (1995) - [c5]Harry Hollander, Bradley S. Carlson, Toby D. Bennett:
Synthesis of SEU-tolerant ASICs using concurrent error correction. Great Lakes Symposium on VLSI 1995: 90-93 - 1994
- [c4]Yuan Hu, Bradley S. Carlson:
A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis. ISCAS 1994: 57-60 - [c3]Yuan Hu, Bradley S. Carlson:
Improved Lower Bounds for the Scheduling Optimization Problem. ISCAS 1994: 295-298 - 1993
- [c2]Bradley S. Carlson, C. Y. Roger Chen:
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. DAC 1993: 361-366 - [c1]Yuan Hu, Ahmed Ghouse, Bradley S. Carlson:
Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs. ICCD 1993: 21-24 - 1991
- [j1]Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh:
Optimal cell generation for dual independent layout styles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 770-782 (1991)
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