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ORCID2. Great Lakes Symposium on VLSI 1992: Kalamazoo, MI, USA
- Proceedings of the Second Great Lakes Symposium on VLSI, Kalamazoo, MI, USA, February 28-29, 1992. IEEE 1992, ISBN 0-8186-2610-0
- P. Johannes, Luc J. M. Claesen, Hugo De Man:
On the use of hierarchy in timing verification with statically sensitizable paths. 4-8 - Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang, Yu-Shen Lin:
A design for concurrent error detections in FPLAs. 9-15 - Oliver F. Haberl, Thomas Kropf:
A chip solution to hierarchical and boundary-scan compatible board level BIST. 16-21 - S. Bapat, James P. Cohoon, Patrick L. Heck, A. Ju, L. J. Randall:
Examining routing solutions. 24-29 - John E. Savage, Markus G. Wloka:
The parallel complexity of minimizing column conflicts. 30-34 - Andrew Lim, Yeow Meng Chee, Ching-Ting Wu:
Performance driven placement with global routing for macro cells. 35-41 - Imtiaz Ahmad, C. Y. Roger Chen:
A heuristic for data path synthesis using multiport memories. 44-51 - Marc Pauwels, Dirk Lanneer, Francky Catthoor, Gert Goossens, Hugo De Man:
Models for bit-true simulation and high-level synthesis of DSP applications. 52-59 - Andrew Seawright, Forrest Brewer
:
High performance data-path synthesis via communication metrics. 60-67 - Heather Booth, Rajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi:
Cutwidth approximation in linear time. 70-73 - Sourav Bhattacharya, Shekhar H. Kirani, Wei-Tek Tsai:
Quadtree interconnection network layout. 74-81 - Antonije D. Jovanovic, Yee Yolk Yeng:
Interactive optimal channel router for critical nets. 84-90 - Kuo-Feng Liao:
Two-layer via-free routing in channels and switchboxes. 91-94 - Tae Won Cho, Sam S. Pyo, J. Robert Heath:
A new conflict resolving switchbox router. 95-102 - Brenda Luderman, Alexander Albicki:
An asynchronous multiplier. 104-108 - John Compton, Alexander Albicki:
Self-timed pipeline with adder. 109-113 - Asjad M. T. Khan, Sadiq M. Sait, Gerhard F. Beckhoff:
VLSI implementation of controllers for communication protocols from their Petri net models. 114-121 - Reza Hashemian:
An alternative algorithm for high speed multiplication and addition using growing technique. 124-129 - Chang N. Zhang, Alen George Law, Ali Rezazadeh:
A systematic approach for designing systolic arrays. 130-137 - Ahmed Riadh Baba-Ali:
A new algorithm for signal flow determination in CMOS VLSI. 138-141 - Jon Hamkins, Donna J. Brown:
Routing in a rectangle with k-ary overlap. 144-151 - Dee Parks, Miroslaw Truszczynski:
An algorithm for embedding a class of non-even routing problems in even routing problems. 152-158 - C.-J. Richard Shi:
A signed hypergraph model of constrained via minimization. 159-166 - Jack Greenbaum, Forrest Brewer:
Interface constrained processor specification and scheduling. 168-175 - Glenn Jennings:
On the detection and elimination of superfluous level-sensitive latches. 176-182 - Xin Hua, Hantao Zhang:
Axiomatic semantics of a hardware specification language. 183-190 - S. Sundaram, Lalit M. Patnaik:
T-algorithm-based logic simulation on distributed systems. 191-195 - Jan-Ming Ho, Ren-Song Tsay:
Clock tree regeneration. 198-203 - Kia Makki, Niki Pissinou:
The Steiner tree problem with minimum number of vertices in graphs. 204-206 - Forbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave:
Optimum Steiner tree generation. 207-212
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