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ORCIDShunji Nakata
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2010 – 2019
- 2017
[j17]Shunji Nakata
, Masaki Ono, Masato Sakitani:
An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor. J. Circuits Syst. Comput. 26(1): 1750007:1-1750007:15 (2017)- 2014
- [j16]Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda:
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. 23(3) (2014) - [j15]Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2194-2203 (2014) - [j14]Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda:
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 686-690 (2014) - [c4]Shunji Nakata, Hiroshi Makino, Yoshio Matsuda:
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. MWSCAS 2014: 439-442 - 2012
- [j13]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6(4): 260-270 (2012) - [j12]Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda:
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2301-2314 (2012) - [c3]Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda:
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. MWSCAS 2012: 1068-1071 - 2011
- [j11]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 230-234 (2011) - 2010
- [j10]Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express 7(9): 640-646 (2010) - [j9]Shunji Nakata, Masayuki Miyama, Yoshio Matsuda:
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. IET Circuits Devices Syst. 4(4): 301-311 (2010) - [c2]Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS 2010: 2474-2477
2000 – 2009
- 2009
- [c1]Shunji Nakata, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda:
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. ISCAS 2009: 393-396 - 2008
- [j8]Shunji Nakata:
Adiabatic quasi 6T-SRAM with shared writing and reading ports. IEICE Electron. Express 5(5): 163-169 (2008) - 2007
- [j7]Shunji Nakata:
Stability of adiabatic reversible charging using 1D-capacitor array between the power supply and ground. IEICE Electron. Express 4(1): 9-14 (2007) - [j6]Shunji Nakata:
Stability of adiabatic circuit using asymmetric 1D-capacitor array between the power supply and ground. IEICE Electron. Express 4(5): 165-171 (2007) - [j5]Shunji Nakata:
Stability of an adiabatic circuit with inductive load using 1D-capacitor array between the power supply and ground. IEICE Electron. Express 4(15): 485-491 (2007) - [j4]Shunji Nakata, Yoshitada Katagiri:
Electrostatic Energy, Potential Energy and Energy Dissipation for a Width-Variable Capacitor Coupled with Mechatronical Potential Energy during Adiabatic Charging. IEICE Trans. Electron. 90-C(1): 139-144 (2007) - 2006
- [j3]Shunji Nakata:
Analysis of the stability of adiabatic reversible logic using the theory of normal modes in coupled oscillators. IEICE Electron. Express 3(2): 17-22 (2006) - [j2]Shunji Nakata:
Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage. IEICE Electron. Express 3(13): 304-309 (2006) - 2005
- [j1]Shunji Nakata:
The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM. IEICE Electron. Express 2(20): 512-518 (2005)
Coauthor Index
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