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ORCIDMohamed Hassan 0002
Person information
- affiliation: McMaster University, Department of Electrical and Computer Engineering, Hamilton, ON, Canad
- affiliation: Intel Corporation, Intel PSG, Toronto, ON, Canada
- affiliation: University of Guelph, ON, Canada
- affiliation (PhD 2017): University of Waterloo, Waterloo, ON, Canada
Other persons with the same name
- Mohamed Hassan — disambiguation page
- Mohamed Hassan 0001
![[0000-0003-3729-4543]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-3729-4543")
(aka: Mohamed G. Hassan 0001) — University of Portsmouth, School of Energy and Electronic Engineering, UK (and 1 more) - Mohamed Hassan 0003 — University of Tübingen, Germany
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Books and Theses
- 2017
[b1]Mohamed Hassan:
Predictable Shared Memory Resources for Multi-Core Real-Time Systems. University of Waterloo, Ontario, Canada, 2017
Journal Articles
- 2023
- [j11]Mohamed Hassan:
DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems. IEEE Trans. Computers 72(4): 1163-1177 (2023) - [j10]Salah Hessien, Mohamed Hassan:
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems. ACM Trans. Embed. Comput. Syst. 22(1): 16:1-16:27 (2023) - 2021
- [j9]Anirudh Mohan Kaushik, Mohamed Hassan, Hiren D. Patel:
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. IEEE Trans. Computers 70(12): 2098-2111 (2021) - 2020
- [j8]Reza Mirosanlou, Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni:
MCsim: An Extensible DRAM Memory Controller Simulator. IEEE Comput. Archit. Lett. 19(2): 105-109 (2020) - [j7]Mohamed Hassan:
Reduced latency DRAM for multi-core safety-critical real-time systems. Real Time Syst. 56(2): 171-206 (2020) - 2018
- [j6]Mohamed Hassan:
Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities. IEEE Des. Test 35(4): 47-55 (2018) - [j5]Mohamed Hassan, Hiren D. Patel:
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1050-1063 (2018) - [j4]Mohamed Hassan, Rodolfo Pellizzoni:
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2323-2336 (2018) - [j3]Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, Hiren D. Patel:
A Comparative Study of Predictable DRAM Controllers. ACM Trans. Embed. Comput. Syst. 17(2): 53:1-53:23 (2018) - [j2]Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. ACM Trans. Embed. Comput. Syst. 17(5): 90:1-90:25 (2018) - 2017
- [j1]Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni:
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. ACM Trans. Embed. Comput. Syst. 16(4): 100:1-100:28 (2017)
Conference and Workshop Papers
- 2024
- [c24]Safin Bayes, Mohamed Hossam, Mohamed Hassan:
Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? DATE 2024: 1-6 - 2023
- [c23]Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, Mohamed Hassan:
A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. ECRTS 2023: 17:1-17:25 - [c22]Asier Fernández de Lecea, Mohamed Hassan, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. RTSS 2023: 265-278 - [c21]Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco Javier Cazorla-Almeida:
Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems. SAC 2023: 461-470 - [c20]Bailian Sun, Safin Bayes, Abdelrhman Mohamed Abotaleb, Mohamed Hassan:
The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation. SAC 2023: 629-638 - 2022
- [c19]Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds. ECRTS 2022: 16:1-16:27 - [c18]Mohamed Hossam, Mohamed Hassan:
Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. ECRTS 2022: 17:1-17:23 - [c17]Khaled Ahmed, Mohamed Hassan:
tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge. ICHI 2022: 264-275 - 2021
- [c16]Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
Duetto: Latency Guarantees at Minimal Performance Cost. DATE 2021: 1136-1141 - [c15]Roger Pujol, Hamid Tabani, Jaume Abella, Mohamed Hassan, Francisco J. Cazorla:
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. DATE 2021: 1162-1165 - [c14]Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla:
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. ICCAD 2021: 1-9 - [c13]Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. MEMSYS 2021: 4:1-4:16 - 2020
- [c12]Mohamed Hassan:
Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems. ECRTS 2020: 16:1-16:24 - [c11]Mohamed Hassan, Rodolfo Pellizzoni:
Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. ECRTS 2020: 23:1-23:24 - [c10]Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. RTAS 2020: 82-94 - [c9]Salah Hessien, Mohamed Hassan:
The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications. RTSS 2020: 218-230 - 2019
- [c8]Mohamed Hassan:
Managing DRAM Interference in Mixed Criticality Embedded Systems. ICM 2019: 253-257 - [c7]Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel:
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. RTSS 2019: 433-445 - 2018
- [c6]Mohamed Hassan:
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? RTSS 2018: 495-505 - 2017
- [c5]Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Predictable Cache Coherence for Multi-core Real-Time Systems. RTAS 2017: 235-246 - 2016
- [c4]Mohamed Hassan, Hiren D. Patel:
MCXplore: An automated framework for validating memory controller designs. DATE 2016: 1357-1362 - [c3]Mohamed Hassan, Hiren D. Patel:
Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. RTAS 2016: 73-83 - 2015
- [c2]Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel:
Reverse-engineering embedded memory controllers through latency-based analysis. RTAS 2015: 297-306 - [c1]Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni:
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. RTAS 2015: 307-316
Informal and Other Publications
- 2018
- [i3]Mohamed Hassan:
On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? CoRR abs/1810.07059 (2018) - 2017
- [i2]Mohamed Hassan:
Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities. CoRR abs/1706.07429 (2017) - [i1]Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel:
HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR abs/1706.07568 (2017)
Coauthor Index
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