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ORCID26th RTAS 2020: Sydney, Australia
- IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020, Sydney, Australia, April 21-24, 2020. IEEE 2020, ISBN 978-1-7281-5499-2
- Seulki Lee
, Shahriar Nirjon:
SubFlow: A Dynamic Induced-Subgraph Strategy Toward Real-Time DNN Inference and Training. 15-29 - Filip Markovic, Jan Carlson, Radu Dobrin:
Cache-aware response time analysis for real-time tasks with fixed preemption points. 30-42 - Seonyeong Heo, Seungbin Song, Bongjun Kim, Hanjun Kim:
Sharing-aware Data Acquisition Scheduling for Multiple Rules in the IoT. 43-55 - Jinghao Sun, Jing Li, Zhishan Guo, An Zou, Xuan Zhang, Kunal Agrawal, Sanjoy K. Baruah:
Real-Time Scheduling upon a Host-Centric Acceleration Architecture with Data Offloading. 56-69 - Haitong Wang, Neil C. Audsley, Wanli Chang:
Addressing Resource Contention and Timing Predictability for Multi-Core Architectures with Shared Memory Interconnects. 70-81 - Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. 82-94 - Bashima Islam, Shahriar Nirjon:
Scheduling Computational and Energy Harvesting Tasks in Deadline-Aware Intermittent Systems. 95-109 - Neeraj Gandhi, Edo Roth, Robert Gifford, Linh Thi Xuan Phan, Andreas Haeberlen:
Bounded-time recovery for distributed real-time systems. 110-123 - Jonathan Falk, Frank Dürr, Kurt Rothermel:
Time-Triggered Traffic Planning for Data Networks with Conflict Graphs. 124-136 - Alan Burns, Leandro Soares Indrusiak, N. Smirnov, J. Harrison:
A Novel Flow Control Mechanism to Avoid Multi-Point Progressive Blocking in Hard Real-Time Priority-Preemptive NoCs. 137-147 - Simon Reder, Jürgen Becker:
Interference-Aware Memory Allocation for Real-Time Multi-Core Systems. 148-159 - Phani Kishore Gadepalli, Runyu Pan, Gabriel Parmer:
Slite: OS Support for Near Zero-Cost, Configurable Scheduling *. 160-173 - Seonyeong Heo, Sungjun Cho, Youngsok Kim, Hanjun Kim:
Real-Time Object Detection System with Multi-Path Neural Networks. 174-187 - Paul Metzger, Murray Cole, Christian Fensch, Marco Aldinucci, Enrico Bini:
Enforcing Deadlines for Skeleton-based Parallel Programming. 188-199 - Dan Iorga, Tyler Sorensen, John Wickerson, Alastair F. Donaldson:
Slow and Steady: Measuring and Tuning Multicore Interference. 200-212 - Ignacio Sanudo Olmedo, Nicola Capodieci, Jorge Luis Martinez, Andrea Marongiu, Marko Bertogna:
Dissecting the CUDA scheduling hierarchy: a Performance and Predictability Perspective. 213-225 - Micaela Verucchi, Mirco Theile, Marco Caccamo, Marko Bertogna:
Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task Sets. 226-238 - Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio C. Buttazzo:
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling. 239-252 - Jeremy Giesen, Pedro Benedicte, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP). 253-266 - Miguel Alcon, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Timing of Autonomous Driving Software: Problem Analysis and Prospects for Future Solutions. 267-280 - Corey Tessler, Venkata P. Modekurthy, Nathan Fisher, Abusayeed Saifullah:
Bringing Inter-Thread Cache Benefits to Federated Scheduling. 281-295 - Shahin Roozkhosh, Renato Mancuso:
The Potential of Programmable Logic in the Middle: Cache Bleaching. 296-309 - Soroush Bateni, Zhendong Wang, Yuankun Zhu, Yang Hu, Cong Liu:
Co-Optimizing Performance and Memory Footprint Via Integrated CPU/GPU Memory Management, an Implementation on Autonomous Driving Platform. 310-323 - Iljoo Baek, Matthew Harding, Akshit Kanda, Kyung Ryeol Choi, Soheil Samii, Ragunathan Raj Rajkumar:
CARSS: Client-Aware Resource Sharing and Scheduling for Heterogeneous Applications. 324-335 - Seyedmehdi Hosseinimotlagh, Ali Ghahremannezhad, Hyoseung Kim:
On Dynamic Thermal Conditions in Mixed-Criticality Systems. 336-349 - Martin Geier, Marian Brändle, Dominik Faller, Samarjit Chakraborty:
Debugging FPGA-accelerated Real-time Systems. 350-363 - Farzad Farshchi, Qijing Huang, Heechul Yun:
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. 364-375 - Arpan Gujarati, Sergey Bozhko, Björn B. Brandenburg:
Real-Time Replica Consistency over Ethernet with Reliability Bounds. 376-389 - Ahmad Golchin, Soham Sinha, Richard West:
Boomerang: Real-Time I/O Meets Legacy Systems. 390-402
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