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Journal Articles
- 2009
[j7]Stanley Schuster, Richard E. Matick:
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier. IEEE J. Solid State Circuits 44(2): 631-641 (2009)- 2008
- [j6]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - 2005
- [j5]Richard E. Matick, Stanley Schuster:
Logic-based eDRAM: Origins and rationale for use. IBM J. Res. Dev. 49(1): 145-166 (2005) - 2003
- [j4]David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas
, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster:
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36(12): 49-58 (2003) - [j3]Stanley Schuster, Peter W. Cook:
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. IEEE J. Solid State Circuits 38(4): 622-630 (2003) - 2000
- [j2]Dale L. Critchlow, Robert H. Dennard, Stanley Schuster:
Design and characteristics of n-channel insulated-gate field-effect transistors. IBM J. Res. Dev. 44(1): 70-83 (2000) - [j1]David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook:
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro 20(6): 26-44 (2000)
Conference and Workshop Papers
- 2007
- [c6]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617 - 2002
- [c5]Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster:
Synchronous Interlocked Pipelines. ASYNC 2002: 3-12 - [c4]Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster:
Tradeoffs in power-efficient issue queue design. ISLPED 2002: 184-189 - [c3]Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas:
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS 2002: 1-17 - 2001
- [c2]Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook:
A circuit level implementation of an adaptive issue queue for power-aware microprocessors. ACM Great Lakes Symposium on VLSI 2001: 73-78 - 2000
- [c1]Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi:
An Adaptive Issue Queue for Reduced Power at High Performance. PACS 2000: 25-39
Coauthor Index
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