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"Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators ..."

Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura (2007)

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DOI: 10.1093/IETFEC/E90-A.12.2810

access: closed

type: Journal Article

metadata version: 2023-03-10

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Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura:
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2810-2817 (2007)

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