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ORCIDJaekwan Kim 0003
Person information
- affiliation: Samsung Electronics, Hwasung, Korea
Other persons with the same name
- Jae-Kwan Kim 0001 — Hanyang University, Vorononi Diagram Research Center, Seoul, South Korea
- Jae-Kwan Kim 0002 (aka: Jae Kwan Kim 0002) — Korea Institute of Science and Technology (KIST), Intelligent Interaction Center, Seoul, Korea
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2000 – 2009
- 2009
[j3]Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim:
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. IEEE J. Solid State Circuits 44(11): 2987-2998 (2009)- 2006
- [j2]Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim
, Jung-Bae Lee, Changhyun Kim, Soo-In Cho:
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE J. Solid State Circuits 41(4): 831-838 (2006) - [c1]Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim:
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC 2006: 527-536 - 2005
- [j1]Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang:
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. IEEE J. Solid State Circuits 40(1): 233-244 (2005)
Coauthor Index
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