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"An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O ..."

Kyu-Hyoun Kim et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696089

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-06

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  - conf/isscc/KimKCPKJPLKSPKC06
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  - https://dblp.org/rec/conf/isscc/KimKCPKJPLKSPKC06
Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim:
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC 2006: 527-536

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