default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID32nd PACT 2023: Vienna, Austria
- 32nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2023, Vienna, Austria, October 21-25, 2023. IEEE 2023, ISBN 979-8-3503-4254-3
- Sawan Singh, Josué Feliu
, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros:
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. 1-13 - Zhen Peng, Rizwan A. Ashraf, Luanzheng Guo, Ruiqin Tian, Gokcen Kestor:
Automatic Code Generation for High-Performance Graph Algorithms. 14-26 - Aditya Agrawal, V. Krishna Nandivada:
UWOmppro: UWOmp++ with Point-to-Point Synchronization, Reduction and Schedules. 27-38 - Alexander Brauckmann, Elizabeth Polgreen, Tobias Grosser, Michael F. P. O'Boyle:
mlirSynth: Automatic, Retargetable Program Raising in Multi-Level IR Using Program Synthesis. 39-50 - Shubdeep Mohapatra, Biswabandan Panda:
Drishyam: An Image is Worth a Data Prefetcher. 51-61 - Weiwei Jia, Jiyuan Zhang, Jianchen Shan, Yiming Du, Xiaoning Ding, Tianyin Xu:
HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address Translation. 62-73 - Hussein Elnawawy, James Tuck, Gregory T. Byrd:
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback. 74-85 - Hyokeun Lee, Kwanseok Choi, Hyuk-Jae Lee, Jaewoong Sim:
SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link. 86-98 - Jinfan Chen, Juan Gómez-Luna, Izzat El Hajj, Yuxin Guo, Onur Mutlu:
SimplePIM: A Software Framework for Productive and Efficient Processing-in-Memory. 99-111 - Donghyeon Kim, Taehoon Kim, Inyong Hwang, Taehyeong Park, Hanjun Kim, Youngsok Kim, Yongjun Park:
Virtual PIM: Resource-Aware Dynamic DPU Allocation and Workload Scheduling Framework for Multi-DPU PIM Architecture. 112-123 - Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González:
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs. 124-136 - Yue Jin, Chengying Huan, Heng Zhang, Yongchao Liu, Shuaiwen Leon Song, Rui Zhao, Yao Zhang, Changhua He, Wenguang Chen:
G-Sparse: Compiler-Driven Acceleration for Generalized Sparse Computation for Graph Neural Networks on Modern GPUs. 137-149 - Giulia Gerometta, Alberto Zeni, Marco D. Santambrogio:
TSUNAMI: A GPU Implementation of the WFA Algorithm. 150-161 - Mohammad Almasri, Yen-Hsiang Chang, Izzat El Hajj, Rakesh Nagi, Jinjun Xiong, Wen-mei W. Hwu:
Parallelizing Maximal Clique Enumeration on GPUs. 162-175 - Jan van Lunteren:
Accelerating Decision-Tree-Based Inference Through Adaptive Parallelization. 176-186 - Louis Narmour, Steven Derrien, Sanjay V. Rajopadhye:
Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations. 187-198 - Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente:
Performance Characterization of Popular DNN Models on Out-of-Order CPUs. 199-210 - Juelin Liu, Sandeep Polisetty, Hui Guan, Marco Serafini:
GraphMini: Accelerating Graph Pattern Matching Using Auxiliary Graphs. 211-224 - Jiyoung An, Esmerald Aliaj, Sang-Woo Jun:
Barad-dur: Near-Storage Accelerator for Training Large Graph Neural Networks. 225-237 - Yuan Li, Ahmed Louri, Avinash Karanth:
A Silicon Photonic Multi-DNN Accelerator. 238-249 - Mahmut Taylan Kandemir, Gulsum Gudukbay Akbulut, Wonil Choi, Mustafa Karaköy:
Architecture-Aware Currying. 250-264 - Zack McKevitt, Ashutosh Trivedi, Tamara Silbergleit Lehman:
SpecCheck: A Tool for Systematic Identification of Vulnerable Transient Execution in gem5. 265-278 - Yaodong Sheng, Ahmed Hassan, Michael F. Spear:
Separating Mechanism from Policy in STM. 279-296 - Hongwei Cui, Yujie Cui, Honglan Zhan, Shuhao Liang, Xianhua Liu, Chun Yang, Xu Cheng:
MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies. 297-308 - Jae Seok Kwak, Myung Kuk Yoon, Ipoom Jeong, Seunghyun Jin, Won Woo Ro:
INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core. 309-319 - Tiago Santos, João Bispo, João M. P. Cardoso:
A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications. 320-322 - Lucia Pons, Julio Sahuquillo, Timothy M. Jones:
Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers. 323-324 - Bahareh Khabbazan, Marc Riera, Antonio González:
QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures. 325-326 - Tayyeb Mahmood, Kashif Inayat, Jaeyong Chung:
Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators. 327-328 - Luís Miguel Sousa, João Bispo, Nuno Paulino:
Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework. 329-331 - Raúl Taranco, José-María Arnau, Antonio González:
SLIDEX: Sliding Window Extension for Image Processing. 332-334 - Marta Navarro, Josué Feliu, Salvador Petit, María Engracia Gómez, Julio Sahuquillo:
Thread-to-Core Allocation in ARM Processors Building Synergistic Pairs. 335-336 - Gwangeun Byeon, Seungtae Lee, Seongwook Kim, Yongjun Kim, Prashant J. Nair, Seokin Hong:
SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs. 337-338
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-22 02:23 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
