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ORCIDKrishnaswamy Nagaraj
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Journal Articles
- 2021
[j21]Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev:
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops. ACM Trans. Design Autom. Electr. Syst. 26(3): 20:1-20:18 (2021)- 2015
- [j20]Xiao Pu, Mikel Ash, Krishnaswamy Nagaraj, Joonsung Park, Steve Vu, Paul Kimelman, Sean de la Haye:
An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4°C (3σ) From - 40°C to 130°C. IEEE J. Solid State Circuits 50(9): 2127-2137 (2015) - 2014
- [j19]Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj:
Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference". IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 639 (2014) - 2013
- [j18]Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun:
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 517-528 (2013) - 2012
- [j17]Xiao Pu, Krishnaswamy Nagaraj, Jacob A. Abraham, Axel Thomsen:
A Novel fractional-n PLL Based on a Simple Reference Multiplier. J. Circuits Syst. Comput. 21(6) (2012) - [j16]Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj:
Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 331-335 (2012) - 2011
- [j15]Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan:
A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 734-738 (2011) - 2007
- [j14]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 42(4): 719 (2007) - [j13]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 42(5): 951 (2007) - [j12]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 42(6): 1195 (2007) - [j11]Krishnaswamy Nagaraj:
New Associate Editors. IEEE J. Solid State Circuits 42(7): 1451-1452 (2007) - [j10]Krishnaswamy Nagaraj:
Message from the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 42(8): 1631 (2007) - 2005
- [j9]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 40(2): 359 (2005) - [j8]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 40(3): 575 (2005) - [j7]Krishnaswamy Nagaraj:
New Associate Editor. IEEE J. Solid State Circuits 40(6): 1211 (2005) - 2004
- [j6]Krishnaswamy Nagaraj:
Editorial. IEEE J. Solid State Circuits 39(8): 1220 (2004) - 2000
- [j5]Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Widely programmable high-frequency continuous-time filters in digital CMOS technology. IEEE J. Solid State Circuits 35(4): 503-511 (2000) - [j4]Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan:
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits 35(12): 1760-1768 (2000) - 1997
- [j3]Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger:
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. IEEE J. Solid State Circuits 32(3): 312-320 (1997) - [j2]Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj:
A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits 32(11): 1858-1865 (1997) - 1995
- [j1]Khong-Meng Tham, Krishnaswamy Nagaraj:
A low supply voltage high PSRR voltage reference in CMOS process. IEEE J. Solid State Circuits 30(5): 586-590 (1995)
Conference and Workshop Papers
- 2019
- [c6]Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev:
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection. ETS 2019: 1-6 - 2017
- [c5]Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar:
A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm using novel residue boosting. CICC 2017: 1-4 - 2016
- [c4]Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano
, Kofi A. A. Makinwa, Krishnaswamy Nagaraj, Joonsung Park:
An oxide electrothermal filter in standard CMOS. IEEE SENSORS 2016: 1-3 - 2014
- [c3]Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan:
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. MWSCAS 2014: 1053-1056 - 2001
- [c2]Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan:
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC 2001: 153-156 - 1999
- [c1]Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ISCAS (6) 1999: 202-205
Coauthor Index
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